1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <functional>
52#include <string>
53#include <vector>
54
55#include "base/logging.hh"
56#include "base/types.hh"
57#include "debug/CacheRepl.hh"
58#include "mem/cache/base.hh"
59#include "mem/cache/blk.hh"
60#include "mem/cache/replacement_policies/base.hh"
61#include "mem/cache/tags/base.hh"
62#include "mem/cache/tags/cacheset.hh"
63#include "mem/packet.hh"
64#include "params/BaseSetAssoc.hh"
65
66/**
67 * A BaseSetAssoc cache tag store.
68 * @sa \ref gem5MemorySystem "gem5 Memory System"
69 *
70 * The BaseSetAssoc placement policy divides the cache into s sets of w
71 * cache lines (ways). A cache line is mapped onto a set, and can be placed
72 * into any of the ways of this set.
73 */
74class BaseSetAssoc : public BaseTags
75{
76 public:
77 /** Typedef the block type used in this tag store. */
78 typedef CacheBlk BlkType;
79 /** Typedef the set type used in this tag store. */
80 typedef CacheSet<CacheBlk> SetType;
81
82 protected:
83 /** The associativity of the cache. */
84 const unsigned assoc;
85 /** The allocatable associativity of the cache (alloc mask). */
86 unsigned allocAssoc;
87
88 /** The cache blocks. */
89 std::vector<BlkType> blks;
90
91 /** The number of sets in the cache. */
92 const unsigned numSets;
93
94 /** Whether tags and data are accessed sequentially. */
95 const bool sequentialAccess;
96
97 /** The cache sets. */
98 std::vector<SetType> sets;
99
100 /** The amount to shift the address to get the set. */
101 int setShift;
102 /** The amount to shift the address to get the tag. */
103 int tagShift;
104 /** Mask out all bits that aren't part of the set index. */
105 unsigned setMask;
106
107 /** Replacement policy */
108 BaseReplacementPolicy *replacementPolicy;
109
110 public:
111 /** Convenience typedef. */
112 typedef BaseSetAssocParams Params;
113
114 /**
115 * Construct and initialize this tag store.
116 */
117 BaseSetAssoc(const Params *p);
118
119 /**
120 * Destructor
121 */
122 virtual ~BaseSetAssoc() {};
123
124 /**
| 1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <functional>
52#include <string>
53#include <vector>
54
55#include "base/logging.hh"
56#include "base/types.hh"
57#include "debug/CacheRepl.hh"
58#include "mem/cache/base.hh"
59#include "mem/cache/blk.hh"
60#include "mem/cache/replacement_policies/base.hh"
61#include "mem/cache/tags/base.hh"
62#include "mem/cache/tags/cacheset.hh"
63#include "mem/packet.hh"
64#include "params/BaseSetAssoc.hh"
65
66/**
67 * A BaseSetAssoc cache tag store.
68 * @sa \ref gem5MemorySystem "gem5 Memory System"
69 *
70 * The BaseSetAssoc placement policy divides the cache into s sets of w
71 * cache lines (ways). A cache line is mapped onto a set, and can be placed
72 * into any of the ways of this set.
73 */
74class BaseSetAssoc : public BaseTags
75{
76 public:
77 /** Typedef the block type used in this tag store. */
78 typedef CacheBlk BlkType;
79 /** Typedef the set type used in this tag store. */
80 typedef CacheSet<CacheBlk> SetType;
81
82 protected:
83 /** The associativity of the cache. */
84 const unsigned assoc;
85 /** The allocatable associativity of the cache (alloc mask). */
86 unsigned allocAssoc;
87
88 /** The cache blocks. */
89 std::vector<BlkType> blks;
90
91 /** The number of sets in the cache. */
92 const unsigned numSets;
93
94 /** Whether tags and data are accessed sequentially. */
95 const bool sequentialAccess;
96
97 /** The cache sets. */
98 std::vector<SetType> sets;
99
100 /** The amount to shift the address to get the set. */
101 int setShift;
102 /** The amount to shift the address to get the tag. */
103 int tagShift;
104 /** Mask out all bits that aren't part of the set index. */
105 unsigned setMask;
106
107 /** Replacement policy */
108 BaseReplacementPolicy *replacementPolicy;
109
110 public:
111 /** Convenience typedef. */
112 typedef BaseSetAssocParams Params;
113
114 /**
115 * Construct and initialize this tag store.
116 */
117 BaseSetAssoc(const Params *p);
118
119 /**
120 * Destructor
121 */
122 virtual ~BaseSetAssoc() {};
123
124 /**
|
125 * This function updates the tags when a block is invalidated but does
126 * not invalidate the block itself. It also updates the replacement data.
| 125 * This function updates the tags when a block is invalidated. It also
126 * updates the replacement data.
|
127 *
128 * @param blk The block to invalidate.
129 */
130 void invalidate(CacheBlk *blk) override;
131
132 /**
133 * Access block and update replacement data. May not succeed, in which case
134 * nullptr is returned. This has all the implications of a cache
135 * access and should only be used as such. Returns the access latency as a
136 * side effect.
137 * @param addr The address to find.
138 * @param is_secure True if the target memory space is secure.
139 * @param lat The access latency.
140 * @return Pointer to the cache block if found.
141 */
142 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
143 {
144 BlkType *blk = findBlock(addr, is_secure);
145
146 // Access all tags in parallel, hence one in each way. The data side
147 // either accesses all blocks in parallel, or one block sequentially on
148 // a hit. Sequential access with a miss doesn't access data.
149 tagAccesses += allocAssoc;
150 if (sequentialAccess) {
151 if (blk != nullptr) {
152 dataAccesses += 1;
153 }
154 } else {
155 dataAccesses += allocAssoc;
156 }
157
158 if (blk != nullptr) {
159 // If a cache hit
160 lat = accessLatency;
161 // Check if the block to be accessed is available. If not,
162 // apply the accessLatency on top of block->whenReady.
163 if (blk->whenReady > curTick() &&
164 cache->ticksToCycles(blk->whenReady - curTick()) >
165 accessLatency) {
166 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
167 accessLatency;
168 }
169
170 // Update number of references to accessed block
171 blk->refCount++;
172
173 // Update replacement data of accessed block
174 replacementPolicy->touch(blk->replacementData);
175 } else {
176 // If a cache miss
177 lat = lookupLatency;
178 }
179
180 return blk;
181 }
182
183 /**
184 * Finds the given address in the cache, do not update replacement data.
185 * i.e. This is a no-side-effect find of a block.
186 * @param addr The address to find.
187 * @param is_secure True if the target memory space is secure.
188 * @param asid The address space ID.
189 * @return Pointer to the cache block if found.
190 */
191 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
192
193 /**
194 * Find a block given set and way.
195 *
196 * @param set The set of the block.
197 * @param way The way of the block.
198 * @return The block.
199 */
200 ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override;
201
202 /**
203 * Find replacement victim based on address. The list of evicted blocks
204 * only contains the victim.
205 *
206 * @param addr Address to find a victim for.
207 * @param evict_blks Cache blocks to be evicted.
208 * @return Cache block to be replaced.
209 */
210 CacheBlk* findVictim(Addr addr, std::vector<CacheBlk*>& evict_blks) const
211 override
212 {
213 // Get possible locations for the victim block
214 std::vector<CacheBlk*> locations = getPossibleLocations(addr);
215
216 // Choose replacement victim from replacement candidates
217 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim(
218 std::vector<ReplaceableEntry*>(
219 locations.begin(), locations.end())));
220
221 // There is only one eviction for this replacement
222 evict_blks.push_back(victim);
223
224 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
225 victim->set, victim->way);
226
227 return victim;
228 }
229
230 /**
231 * Find all possible block locations for insertion and replacement of
232 * an address. Should be called immediately before ReplacementPolicy's
233 * findVictim() not to break cache resizing.
234 * Returns blocks in all ways belonging to the set of the address.
235 *
236 * @param addr The addr to a find possible locations for.
237 * @return The possible locations.
238 */
239 const std::vector<CacheBlk*> getPossibleLocations(Addr addr) const
240 {
241 return sets[extractSet(addr)].blks;
242 }
243
244 /**
245 * Insert the new block into the cache and update replacement data.
246 *
247 * @param pkt Packet holding the address to update
248 * @param blk The block to update.
249 */
250 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
251 {
252 // Insert block
253 BaseTags::insertBlock(pkt, blk);
254
| 127 *
128 * @param blk The block to invalidate.
129 */
130 void invalidate(CacheBlk *blk) override;
131
132 /**
133 * Access block and update replacement data. May not succeed, in which case
134 * nullptr is returned. This has all the implications of a cache
135 * access and should only be used as such. Returns the access latency as a
136 * side effect.
137 * @param addr The address to find.
138 * @param is_secure True if the target memory space is secure.
139 * @param lat The access latency.
140 * @return Pointer to the cache block if found.
141 */
142 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
143 {
144 BlkType *blk = findBlock(addr, is_secure);
145
146 // Access all tags in parallel, hence one in each way. The data side
147 // either accesses all blocks in parallel, or one block sequentially on
148 // a hit. Sequential access with a miss doesn't access data.
149 tagAccesses += allocAssoc;
150 if (sequentialAccess) {
151 if (blk != nullptr) {
152 dataAccesses += 1;
153 }
154 } else {
155 dataAccesses += allocAssoc;
156 }
157
158 if (blk != nullptr) {
159 // If a cache hit
160 lat = accessLatency;
161 // Check if the block to be accessed is available. If not,
162 // apply the accessLatency on top of block->whenReady.
163 if (blk->whenReady > curTick() &&
164 cache->ticksToCycles(blk->whenReady - curTick()) >
165 accessLatency) {
166 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
167 accessLatency;
168 }
169
170 // Update number of references to accessed block
171 blk->refCount++;
172
173 // Update replacement data of accessed block
174 replacementPolicy->touch(blk->replacementData);
175 } else {
176 // If a cache miss
177 lat = lookupLatency;
178 }
179
180 return blk;
181 }
182
183 /**
184 * Finds the given address in the cache, do not update replacement data.
185 * i.e. This is a no-side-effect find of a block.
186 * @param addr The address to find.
187 * @param is_secure True if the target memory space is secure.
188 * @param asid The address space ID.
189 * @return Pointer to the cache block if found.
190 */
191 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
192
193 /**
194 * Find a block given set and way.
195 *
196 * @param set The set of the block.
197 * @param way The way of the block.
198 * @return The block.
199 */
200 ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override;
201
202 /**
203 * Find replacement victim based on address. The list of evicted blocks
204 * only contains the victim.
205 *
206 * @param addr Address to find a victim for.
207 * @param evict_blks Cache blocks to be evicted.
208 * @return Cache block to be replaced.
209 */
210 CacheBlk* findVictim(Addr addr, std::vector<CacheBlk*>& evict_blks) const
211 override
212 {
213 // Get possible locations for the victim block
214 std::vector<CacheBlk*> locations = getPossibleLocations(addr);
215
216 // Choose replacement victim from replacement candidates
217 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim(
218 std::vector<ReplaceableEntry*>(
219 locations.begin(), locations.end())));
220
221 // There is only one eviction for this replacement
222 evict_blks.push_back(victim);
223
224 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
225 victim->set, victim->way);
226
227 return victim;
228 }
229
230 /**
231 * Find all possible block locations for insertion and replacement of
232 * an address. Should be called immediately before ReplacementPolicy's
233 * findVictim() not to break cache resizing.
234 * Returns blocks in all ways belonging to the set of the address.
235 *
236 * @param addr The addr to a find possible locations for.
237 * @return The possible locations.
238 */
239 const std::vector<CacheBlk*> getPossibleLocations(Addr addr) const
240 {
241 return sets[extractSet(addr)].blks;
242 }
243
244 /**
245 * Insert the new block into the cache and update replacement data.
246 *
247 * @param pkt Packet holding the address to update
248 * @param blk The block to update.
249 */
250 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
251 {
252 // Insert block
253 BaseTags::insertBlock(pkt, blk);
254
|
| 255 // Increment tag counter
256 tagsInUse++;
257
|
255 // Update replacement policy
256 replacementPolicy->reset(blk->replacementData);
257 }
258
259 /**
260 * Limit the allocation for the cache ways.
261 * @param ways The maximum number of ways available for replacement.
262 */
263 virtual void setWayAllocationMax(int ways) override
264 {
265 fatal_if(ways < 1, "Allocation limit must be greater than zero");
266 allocAssoc = ways;
267 }
268
269 /**
270 * Get the way allocation mask limit.
271 * @return The maximum number of ways available for replacement.
272 */
273 virtual int getWayAllocationMax() const override
274 {
275 return allocAssoc;
276 }
277
278 /**
279 * Generate the tag from the given address.
280 * @param addr The address to get the tag from.
281 * @return The tag of the address.
282 */
283 Addr extractTag(Addr addr) const override
284 {
285 return (addr >> tagShift);
286 }
287
288 /**
289 * Regenerate the block address from the tag and set.
290 *
291 * @param block The block.
292 * @return the block address.
293 */
294 Addr regenerateBlkAddr(const CacheBlk* blk) const override
295 {
296 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
297 }
298
299 void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
300 for (CacheBlk& blk : blks) {
301 visitor(blk);
302 }
303 }
304
305 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
306 for (CacheBlk& blk : blks) {
307 if (visitor(blk)) {
308 return true;
309 }
310 }
311 return false;
312 }
313
314 private:
315 /**
316 * Calculate the set index from the address.
317 *
318 * @param addr The address to get the set from.
319 * @return The set index of the address.
320 */
321 int extractSet(Addr addr) const
322 {
323 return ((addr >> setShift) & setMask);
324 }
325};
326
327#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
| 258 // Update replacement policy
259 replacementPolicy->reset(blk->replacementData);
260 }
261
262 /**
263 * Limit the allocation for the cache ways.
264 * @param ways The maximum number of ways available for replacement.
265 */
266 virtual void setWayAllocationMax(int ways) override
267 {
268 fatal_if(ways < 1, "Allocation limit must be greater than zero");
269 allocAssoc = ways;
270 }
271
272 /**
273 * Get the way allocation mask limit.
274 * @return The maximum number of ways available for replacement.
275 */
276 virtual int getWayAllocationMax() const override
277 {
278 return allocAssoc;
279 }
280
281 /**
282 * Generate the tag from the given address.
283 * @param addr The address to get the tag from.
284 * @return The tag of the address.
285 */
286 Addr extractTag(Addr addr) const override
287 {
288 return (addr >> tagShift);
289 }
290
291 /**
292 * Regenerate the block address from the tag and set.
293 *
294 * @param block The block.
295 * @return the block address.
296 */
297 Addr regenerateBlkAddr(const CacheBlk* blk) const override
298 {
299 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
300 }
301
302 void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
303 for (CacheBlk& blk : blks) {
304 visitor(blk);
305 }
306 }
307
308 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
309 for (CacheBlk& blk : blks) {
310 if (visitor(blk)) {
311 return true;
312 }
313 }
314 return false;
315 }
316
317 private:
318 /**
319 * Calculate the set index from the address.
320 *
321 * @param addr The address to get the set from.
322 * @return The set index of the address.
323 */
324 int extractSet(Addr addr) const
325 {
326 return ((addr >> setShift) & setMask);
327 }
328};
329
330#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
|