1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <functional>
52#include <string>
53#include <vector>
54
55#include "base/logging.hh"
56#include "base/types.hh"
57#include "debug/CacheRepl.hh"
58#include "mem/cache/base.hh"
59#include "mem/cache/blk.hh"
60#include "mem/cache/replacement_policies/base.hh"
61#include "mem/cache/tags/base.hh"
62#include "mem/cache/tags/cacheset.hh"
63#include "mem/packet.hh"
64#include "params/BaseSetAssoc.hh"
65
66/**
67 * A BaseSetAssoc cache tag store.
68 * @sa \ref gem5MemorySystem "gem5 Memory System"
69 *
70 * The BaseSetAssoc placement policy divides the cache into s sets of w
71 * cache lines (ways). A cache line is mapped onto a set, and can be placed
72 * into any of the ways of this set.
73 */
74class BaseSetAssoc : public BaseTags
75{
76 public:
77 /** Typedef the block type used in this tag store. */
78 typedef CacheBlk BlkType;
79 /** Typedef the set type used in this tag store. */
80 typedef CacheSet<CacheBlk> SetType;
81
82 protected:
83 /** The associativity of the cache. */
84 const unsigned assoc;
85 /** The allocatable associativity of the cache (alloc mask). */
86 unsigned allocAssoc;
87
88 /** The cache blocks. */
89 std::vector<BlkType> blks;
90
91 /** The number of sets in the cache. */
92 const unsigned numSets;
93
94 /** Whether tags and data are accessed sequentially. */
95 const bool sequentialAccess;
96
97 /** The cache sets. */
98 std::vector<SetType> sets;
99
100 /** The amount to shift the address to get the set. */
101 int setShift;
102 /** The amount to shift the address to get the tag. */
103 int tagShift;
104 /** Mask out all bits that aren't part of the set index. */
105 unsigned setMask;
106
107 /** Replacement policy */
108 BaseReplacementPolicy *replacementPolicy;
109
110 public:
111 /** Convenience typedef. */
112 typedef BaseSetAssocParams Params;
113
114 /**
115 * Construct and initialize this tag store.
116 */
117 BaseSetAssoc(const Params *p);
118
119 /**
120 * Destructor
121 */
122 virtual ~BaseSetAssoc() {};
123
124 /**
125 * This function updates the tags when a block is invalidated but does
126 * not invalidate the block itself. It also updates the replacement data.
127 *
128 * @param blk The block to invalidate.
129 */
130 void invalidate(CacheBlk *blk) override;
131
132 /**
| 1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <functional>
52#include <string>
53#include <vector>
54
55#include "base/logging.hh"
56#include "base/types.hh"
57#include "debug/CacheRepl.hh"
58#include "mem/cache/base.hh"
59#include "mem/cache/blk.hh"
60#include "mem/cache/replacement_policies/base.hh"
61#include "mem/cache/tags/base.hh"
62#include "mem/cache/tags/cacheset.hh"
63#include "mem/packet.hh"
64#include "params/BaseSetAssoc.hh"
65
66/**
67 * A BaseSetAssoc cache tag store.
68 * @sa \ref gem5MemorySystem "gem5 Memory System"
69 *
70 * The BaseSetAssoc placement policy divides the cache into s sets of w
71 * cache lines (ways). A cache line is mapped onto a set, and can be placed
72 * into any of the ways of this set.
73 */
74class BaseSetAssoc : public BaseTags
75{
76 public:
77 /** Typedef the block type used in this tag store. */
78 typedef CacheBlk BlkType;
79 /** Typedef the set type used in this tag store. */
80 typedef CacheSet<CacheBlk> SetType;
81
82 protected:
83 /** The associativity of the cache. */
84 const unsigned assoc;
85 /** The allocatable associativity of the cache (alloc mask). */
86 unsigned allocAssoc;
87
88 /** The cache blocks. */
89 std::vector<BlkType> blks;
90
91 /** The number of sets in the cache. */
92 const unsigned numSets;
93
94 /** Whether tags and data are accessed sequentially. */
95 const bool sequentialAccess;
96
97 /** The cache sets. */
98 std::vector<SetType> sets;
99
100 /** The amount to shift the address to get the set. */
101 int setShift;
102 /** The amount to shift the address to get the tag. */
103 int tagShift;
104 /** Mask out all bits that aren't part of the set index. */
105 unsigned setMask;
106
107 /** Replacement policy */
108 BaseReplacementPolicy *replacementPolicy;
109
110 public:
111 /** Convenience typedef. */
112 typedef BaseSetAssocParams Params;
113
114 /**
115 * Construct and initialize this tag store.
116 */
117 BaseSetAssoc(const Params *p);
118
119 /**
120 * Destructor
121 */
122 virtual ~BaseSetAssoc() {};
123
124 /**
125 * This function updates the tags when a block is invalidated but does
126 * not invalidate the block itself. It also updates the replacement data.
127 *
128 * @param blk The block to invalidate.
129 */
130 void invalidate(CacheBlk *blk) override;
131
132 /**
|
133 * Find the cache block given set and way
134 * @param set The set of the block.
135 * @param way The way of the block.
136 * @return The cache block.
137 */
138 CacheBlk *findBlockBySetAndWay(int set, int way) const override;
139
140 /**
| |
141 * Access block and update replacement data. May not succeed, in which case
142 * nullptr is returned. This has all the implications of a cache
143 * access and should only be used as such. Returns the access latency as a
144 * side effect.
145 * @param addr The address to find.
146 * @param is_secure True if the target memory space is secure.
147 * @param lat The access latency.
148 * @return Pointer to the cache block if found.
149 */
150 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
151 {
152 BlkType *blk = findBlock(addr, is_secure);
153
154 // Access all tags in parallel, hence one in each way. The data side
155 // either accesses all blocks in parallel, or one block sequentially on
156 // a hit. Sequential access with a miss doesn't access data.
157 tagAccesses += allocAssoc;
158 if (sequentialAccess) {
159 if (blk != nullptr) {
160 dataAccesses += 1;
161 }
162 } else {
163 dataAccesses += allocAssoc;
164 }
165
166 if (blk != nullptr) {
167 // If a cache hit
168 lat = accessLatency;
169 // Check if the block to be accessed is available. If not,
170 // apply the accessLatency on top of block->whenReady.
171 if (blk->whenReady > curTick() &&
172 cache->ticksToCycles(blk->whenReady - curTick()) >
173 accessLatency) {
174 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
175 accessLatency;
176 }
177
178 // Update number of references to accessed block
179 blk->refCount++;
180
181 // Update replacement data of accessed block
182 replacementPolicy->touch(blk->replacementData);
183 } else {
184 // If a cache miss
185 lat = lookupLatency;
186 }
187
188 return blk;
189 }
190
191 /**
192 * Finds the given address in the cache, do not update replacement data.
193 * i.e. This is a no-side-effect find of a block.
194 * @param addr The address to find.
195 * @param is_secure True if the target memory space is secure.
196 * @param asid The address space ID.
197 * @return Pointer to the cache block if found.
198 */
199 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
200
201 /**
| 133 * Access block and update replacement data. May not succeed, in which case
134 * nullptr is returned. This has all the implications of a cache
135 * access and should only be used as such. Returns the access latency as a
136 * side effect.
137 * @param addr The address to find.
138 * @param is_secure True if the target memory space is secure.
139 * @param lat The access latency.
140 * @return Pointer to the cache block if found.
141 */
142 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
143 {
144 BlkType *blk = findBlock(addr, is_secure);
145
146 // Access all tags in parallel, hence one in each way. The data side
147 // either accesses all blocks in parallel, or one block sequentially on
148 // a hit. Sequential access with a miss doesn't access data.
149 tagAccesses += allocAssoc;
150 if (sequentialAccess) {
151 if (blk != nullptr) {
152 dataAccesses += 1;
153 }
154 } else {
155 dataAccesses += allocAssoc;
156 }
157
158 if (blk != nullptr) {
159 // If a cache hit
160 lat = accessLatency;
161 // Check if the block to be accessed is available. If not,
162 // apply the accessLatency on top of block->whenReady.
163 if (blk->whenReady > curTick() &&
164 cache->ticksToCycles(blk->whenReady - curTick()) >
165 accessLatency) {
166 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
167 accessLatency;
168 }
169
170 // Update number of references to accessed block
171 blk->refCount++;
172
173 // Update replacement data of accessed block
174 replacementPolicy->touch(blk->replacementData);
175 } else {
176 // If a cache miss
177 lat = lookupLatency;
178 }
179
180 return blk;
181 }
182
183 /**
184 * Finds the given address in the cache, do not update replacement data.
185 * i.e. This is a no-side-effect find of a block.
186 * @param addr The address to find.
187 * @param is_secure True if the target memory space is secure.
188 * @param asid The address space ID.
189 * @return Pointer to the cache block if found.
190 */
191 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
192
193 /**
|
| 194 * Find a block given set and way.
195 *
196 * @param set The set of the block.
197 * @param way The way of the block.
198 * @return The block.
199 */
200 ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override;
201
202 /**
|
202 * Find replacement victim based on address.
203 *
204 * @param addr Address to find a victim for.
205 * @return Cache block to be replaced.
206 */
207 CacheBlk* findVictim(Addr addr) override
208 {
209 // Get possible locations for the victim block
210 std::vector<CacheBlk*> locations = getPossibleLocations(addr);
211
212 // Choose replacement victim from replacement candidates
213 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim(
214 std::vector<ReplaceableEntry*>(
215 locations.begin(), locations.end())));
216
217 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
218 victim->set, victim->way);
219
220 return victim;
221 }
222
223 /**
224 * Find all possible block locations for insertion and replacement of
225 * an address. Should be called immediately before ReplacementPolicy's
226 * findVictim() not to break cache resizing.
227 * Returns blocks in all ways belonging to the set of the address.
228 *
229 * @param addr The addr to a find possible locations for.
230 * @return The possible locations.
231 */
232 const std::vector<CacheBlk*> getPossibleLocations(Addr addr)
233 {
234 return sets[extractSet(addr)].blks;
235 }
236
237 /**
238 * Insert the new block into the cache and update replacement data.
239 *
240 * @param pkt Packet holding the address to update
241 * @param blk The block to update.
242 */
243 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
244 {
245 // Insert block
246 BaseTags::insertBlock(pkt, blk);
247
248 // Update replacement policy
249 replacementPolicy->reset(blk->replacementData);
250 }
251
252 /**
253 * Limit the allocation for the cache ways.
254 * @param ways The maximum number of ways available for replacement.
255 */
256 virtual void setWayAllocationMax(int ways) override
257 {
258 fatal_if(ways < 1, "Allocation limit must be greater than zero");
259 allocAssoc = ways;
260 }
261
262 /**
263 * Get the way allocation mask limit.
264 * @return The maximum number of ways available for replacement.
265 */
266 virtual int getWayAllocationMax() const override
267 {
268 return allocAssoc;
269 }
270
271 /**
272 * Generate the tag from the given address.
273 * @param addr The address to get the tag from.
274 * @return The tag of the address.
275 */
276 Addr extractTag(Addr addr) const override
277 {
278 return (addr >> tagShift);
279 }
280
281 /**
282 * Regenerate the block address from the tag and set.
283 *
284 * @param block The block.
285 * @return the block address.
286 */
287 Addr regenerateBlkAddr(const CacheBlk* blk) const override
288 {
289 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
290 }
291
292 void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
293 for (CacheBlk& blk : blks) {
294 visitor(blk);
295 }
296 }
297
298 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
299 for (CacheBlk& blk : blks) {
300 if (visitor(blk)) {
301 return true;
302 }
303 }
304 return false;
305 }
306
307 private:
308 /**
309 * Calculate the set index from the address.
310 *
311 * @param addr The address to get the set from.
312 * @return The set index of the address.
313 */
314 int extractSet(Addr addr) const
315 {
316 return ((addr >> setShift) & setMask);
317 }
318};
319
320#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
| 203 * Find replacement victim based on address.
204 *
205 * @param addr Address to find a victim for.
206 * @return Cache block to be replaced.
207 */
208 CacheBlk* findVictim(Addr addr) override
209 {
210 // Get possible locations for the victim block
211 std::vector<CacheBlk*> locations = getPossibleLocations(addr);
212
213 // Choose replacement victim from replacement candidates
214 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim(
215 std::vector<ReplaceableEntry*>(
216 locations.begin(), locations.end())));
217
218 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
219 victim->set, victim->way);
220
221 return victim;
222 }
223
224 /**
225 * Find all possible block locations for insertion and replacement of
226 * an address. Should be called immediately before ReplacementPolicy's
227 * findVictim() not to break cache resizing.
228 * Returns blocks in all ways belonging to the set of the address.
229 *
230 * @param addr The addr to a find possible locations for.
231 * @return The possible locations.
232 */
233 const std::vector<CacheBlk*> getPossibleLocations(Addr addr)
234 {
235 return sets[extractSet(addr)].blks;
236 }
237
238 /**
239 * Insert the new block into the cache and update replacement data.
240 *
241 * @param pkt Packet holding the address to update
242 * @param blk The block to update.
243 */
244 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
245 {
246 // Insert block
247 BaseTags::insertBlock(pkt, blk);
248
249 // Update replacement policy
250 replacementPolicy->reset(blk->replacementData);
251 }
252
253 /**
254 * Limit the allocation for the cache ways.
255 * @param ways The maximum number of ways available for replacement.
256 */
257 virtual void setWayAllocationMax(int ways) override
258 {
259 fatal_if(ways < 1, "Allocation limit must be greater than zero");
260 allocAssoc = ways;
261 }
262
263 /**
264 * Get the way allocation mask limit.
265 * @return The maximum number of ways available for replacement.
266 */
267 virtual int getWayAllocationMax() const override
268 {
269 return allocAssoc;
270 }
271
272 /**
273 * Generate the tag from the given address.
274 * @param addr The address to get the tag from.
275 * @return The tag of the address.
276 */
277 Addr extractTag(Addr addr) const override
278 {
279 return (addr >> tagShift);
280 }
281
282 /**
283 * Regenerate the block address from the tag and set.
284 *
285 * @param block The block.
286 * @return the block address.
287 */
288 Addr regenerateBlkAddr(const CacheBlk* blk) const override
289 {
290 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
291 }
292
293 void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
294 for (CacheBlk& blk : blks) {
295 visitor(blk);
296 }
297 }
298
299 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
300 for (CacheBlk& blk : blks) {
301 if (visitor(blk)) {
302 return true;
303 }
304 }
305 return false;
306 }
307
308 private:
309 /**
310 * Calculate the set index from the address.
311 *
312 * @param addr The address to get the set from.
313 * @return The set index of the address.
314 */
315 int extractSet(Addr addr) const
316 {
317 return ((addr >> setShift) & setMask);
318 }
319};
320
321#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
|