1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <cassert>
52#include <cstring>
| 1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <cassert>
52#include <cstring>
|
53#include <memory>
| |
54#include <vector>
55
| 53#include <vector>
54
|
| 55#include "debug/CacheRepl.hh"
|
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
| 56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
|
| 58#include "mem/cache/replacement_policies/base.hh"
|
58#include "mem/cache/tags/base.hh"
59#include "mem/cache/tags/cacheset.hh"
60#include "mem/packet.hh"
61#include "params/BaseSetAssoc.hh"
62
63/**
64 * A BaseSetAssoc cache tag store.
65 * @sa \ref gem5MemorySystem "gem5 Memory System"
66 *
67 * The BaseSetAssoc placement policy divides the cache into s sets of w
68 * cache lines (ways). A cache line is mapped onto a set, and can be placed
69 * into any of the ways of this set.
70 */
71class BaseSetAssoc : public BaseTags
72{
73 public:
74 /** Typedef the block type used in this tag store. */
75 typedef CacheBlk BlkType;
76 /** Typedef the set type used in this tag store. */
77 typedef CacheSet<CacheBlk> SetType;
78
79 protected:
80 /** The associativity of the cache. */
81 const unsigned assoc;
82 /** The allocatable associativity of the cache (alloc mask). */
83 unsigned allocAssoc;
84
85 /** The cache blocks. */
86 std::vector<BlkType> blks;
87
88 /** The number of sets in the cache. */
89 const unsigned numSets;
90
91 /** Whether tags and data are accessed sequentially. */
92 const bool sequentialAccess;
93
94 /** The cache sets. */
95 std::vector<SetType> sets;
96
97 /** The amount to shift the address to get the set. */
98 int setShift;
99 /** The amount to shift the address to get the tag. */
100 int tagShift;
101 /** Mask out all bits that aren't part of the set index. */
102 unsigned setMask;
103
104 /** Replacement policy */
105 BaseReplacementPolicy *replacementPolicy;
106
107 public:
| 59#include "mem/cache/tags/base.hh"
60#include "mem/cache/tags/cacheset.hh"
61#include "mem/packet.hh"
62#include "params/BaseSetAssoc.hh"
63
64/**
65 * A BaseSetAssoc cache tag store.
66 * @sa \ref gem5MemorySystem "gem5 Memory System"
67 *
68 * The BaseSetAssoc placement policy divides the cache into s sets of w
69 * cache lines (ways). A cache line is mapped onto a set, and can be placed
70 * into any of the ways of this set.
71 */
72class BaseSetAssoc : public BaseTags
73{
74 public:
75 /** Typedef the block type used in this tag store. */
76 typedef CacheBlk BlkType;
77 /** Typedef the set type used in this tag store. */
78 typedef CacheSet<CacheBlk> SetType;
79
80 protected:
81 /** The associativity of the cache. */
82 const unsigned assoc;
83 /** The allocatable associativity of the cache (alloc mask). */
84 unsigned allocAssoc;
85
86 /** The cache blocks. */
87 std::vector<BlkType> blks;
88
89 /** The number of sets in the cache. */
90 const unsigned numSets;
91
92 /** Whether tags and data are accessed sequentially. */
93 const bool sequentialAccess;
94
95 /** The cache sets. */
96 std::vector<SetType> sets;
97
98 /** The amount to shift the address to get the set. */
99 int setShift;
100 /** The amount to shift the address to get the tag. */
101 int tagShift;
102 /** Mask out all bits that aren't part of the set index. */
103 unsigned setMask;
104
105 /** Replacement policy */
106 BaseReplacementPolicy *replacementPolicy;
107
108 public:
|
108
| |
109 /** Convenience typedef. */
110 typedef BaseSetAssocParams Params;
111
112 /**
113 * Construct and initialize this tag store.
114 */
115 BaseSetAssoc(const Params *p);
116
117 /**
118 * Destructor
119 */
120 virtual ~BaseSetAssoc() {};
121
122 /**
| 109 /** Convenience typedef. */
110 typedef BaseSetAssocParams Params;
111
112 /**
113 * Construct and initialize this tag store.
114 */
115 BaseSetAssoc(const Params *p);
116
117 /**
118 * Destructor
119 */
120 virtual ~BaseSetAssoc() {};
121
122 /**
|
| 123 * This function updates the tags when a block is invalidated but does
124 * not invalidate the block itself. It also updates the replacement data.
125 *
126 * @param blk The block to invalidate.
127 */
128 void invalidate(CacheBlk *blk) override;
129
130 /**
|
123 * Find the cache block given set and way
124 * @param set The set of the block.
125 * @param way The way of the block.
126 * @return The cache block.
127 */
128 CacheBlk *findBlockBySetAndWay(int set, int way) const override;
129
130 /**
131 * Access block and update replacement data. May not succeed, in which case
132 * nullptr is returned. This has all the implications of a cache
133 * access and should only be used as such. Returns the access latency as a
134 * side effect.
135 * @param addr The address to find.
136 * @param is_secure True if the target memory space is secure.
137 * @param lat The access latency.
138 * @return Pointer to the cache block if found.
139 */
140 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
141 {
142 BlkType *blk = findBlock(addr, is_secure);
143
144 // Access all tags in parallel, hence one in each way. The data side
145 // either accesses all blocks in parallel, or one block sequentially on
146 // a hit. Sequential access with a miss doesn't access data.
147 tagAccesses += allocAssoc;
148 if (sequentialAccess) {
149 if (blk != nullptr) {
150 dataAccesses += 1;
151 }
152 } else {
153 dataAccesses += allocAssoc;
154 }
155
156 if (blk != nullptr) {
157 // If a cache hit
158 lat = accessLatency;
159 // Check if the block to be accessed is available. If not,
160 // apply the accessLatency on top of block->whenReady.
161 if (blk->whenReady > curTick() &&
162 cache->ticksToCycles(blk->whenReady - curTick()) >
163 accessLatency) {
164 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
165 accessLatency;
166 }
167
| 131 * Find the cache block given set and way
132 * @param set The set of the block.
133 * @param way The way of the block.
134 * @return The cache block.
135 */
136 CacheBlk *findBlockBySetAndWay(int set, int way) const override;
137
138 /**
139 * Access block and update replacement data. May not succeed, in which case
140 * nullptr is returned. This has all the implications of a cache
141 * access and should only be used as such. Returns the access latency as a
142 * side effect.
143 * @param addr The address to find.
144 * @param is_secure True if the target memory space is secure.
145 * @param lat The access latency.
146 * @return Pointer to the cache block if found.
147 */
148 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
149 {
150 BlkType *blk = findBlock(addr, is_secure);
151
152 // Access all tags in parallel, hence one in each way. The data side
153 // either accesses all blocks in parallel, or one block sequentially on
154 // a hit. Sequential access with a miss doesn't access data.
155 tagAccesses += allocAssoc;
156 if (sequentialAccess) {
157 if (blk != nullptr) {
158 dataAccesses += 1;
159 }
160 } else {
161 dataAccesses += allocAssoc;
162 }
163
164 if (blk != nullptr) {
165 // If a cache hit
166 lat = accessLatency;
167 // Check if the block to be accessed is available. If not,
168 // apply the accessLatency on top of block->whenReady.
169 if (blk->whenReady > curTick() &&
170 cache->ticksToCycles(blk->whenReady - curTick()) >
171 accessLatency) {
172 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
173 accessLatency;
174 }
175
|
| 176 // Update number of references to accessed block
177 blk->refCount++;
178
|
168 // Update replacement data of accessed block
| 179 // Update replacement data of accessed block
|
169 replacementPolicy->touch(blk);
| 180 replacementPolicy->touch(blk->replacementData);
|
170 } else {
171 // If a cache miss
172 lat = lookupLatency;
173 }
174
175 return blk;
176 }
177
178 /**
179 * Finds the given address in the cache, do not update replacement data.
180 * i.e. This is a no-side-effect find of a block.
181 * @param addr The address to find.
182 * @param is_secure True if the target memory space is secure.
183 * @param asid The address space ID.
184 * @return Pointer to the cache block if found.
185 */
186 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
187
188 /**
189 * Find replacement victim based on address.
190 *
191 * @param addr Address to find a victim for.
192 * @return Cache block to be replaced.
193 */
194 CacheBlk* findVictim(Addr addr) override
195 {
| 181 } else {
182 // If a cache miss
183 lat = lookupLatency;
184 }
185
186 return blk;
187 }
188
189 /**
190 * Finds the given address in the cache, do not update replacement data.
191 * i.e. This is a no-side-effect find of a block.
192 * @param addr The address to find.
193 * @param is_secure True if the target memory space is secure.
194 * @param asid The address space ID.
195 * @return Pointer to the cache block if found.
196 */
197 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
198
199 /**
200 * Find replacement victim based on address.
201 *
202 * @param addr Address to find a victim for.
203 * @return Cache block to be replaced.
204 */
205 CacheBlk* findVictim(Addr addr) override
206 {
|
| 207 // Get possible locations for the victim block
208 std::vector<CacheBlk*> locations = getPossibleLocations(addr);
209
|
196 // Choose replacement victim from replacement candidates
| 210 // Choose replacement victim from replacement candidates
|
197 return replacementPolicy->getVictim(getPossibleLocations(addr));
| 211 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim(
212 std::vector<ReplaceableEntry*>(
213 locations.begin(), locations.end())));
214
215 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
216 victim->set, victim->way);
217
218 return victim;
|
198 }
199
200 /**
201 * Find all possible block locations for insertion and replacement of
202 * an address. Should be called immediately before ReplacementPolicy's
203 * findVictim() not to break cache resizing.
204 * Returns blocks in all ways belonging to the set of the address.
205 *
206 * @param addr The addr to a find possible locations for.
207 * @return The possible locations.
208 */
209 const std::vector<CacheBlk*> getPossibleLocations(Addr addr)
210 {
211 return sets[extractSet(addr)].blks;
212 }
213
214 /**
215 * Insert the new block into the cache and update replacement data.
216 *
217 * @param pkt Packet holding the address to update
218 * @param blk The block to update.
219 */
220 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
221 {
222 // Insert block
223 BaseTags::insertBlock(pkt, blk);
224
225 // Update replacement policy
| 219 }
220
221 /**
222 * Find all possible block locations for insertion and replacement of
223 * an address. Should be called immediately before ReplacementPolicy's
224 * findVictim() not to break cache resizing.
225 * Returns blocks in all ways belonging to the set of the address.
226 *
227 * @param addr The addr to a find possible locations for.
228 * @return The possible locations.
229 */
230 const std::vector<CacheBlk*> getPossibleLocations(Addr addr)
231 {
232 return sets[extractSet(addr)].blks;
233 }
234
235 /**
236 * Insert the new block into the cache and update replacement data.
237 *
238 * @param pkt Packet holding the address to update
239 * @param blk The block to update.
240 */
241 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
242 {
243 // Insert block
244 BaseTags::insertBlock(pkt, blk);
245
246 // Update replacement policy
|
226 replacementPolicy->reset(blk);
| 247 replacementPolicy->reset(blk->replacementData);
|
227 }
228
229 /**
230 * Limit the allocation for the cache ways.
231 * @param ways The maximum number of ways available for replacement.
232 */
233 virtual void setWayAllocationMax(int ways) override
234 {
235 fatal_if(ways < 1, "Allocation limit must be greater than zero");
236 allocAssoc = ways;
237 }
238
239 /**
240 * Get the way allocation mask limit.
241 * @return The maximum number of ways available for replacement.
242 */
243 virtual int getWayAllocationMax() const override
244 {
245 return allocAssoc;
246 }
247
248 /**
249 * Generate the tag from the given address.
250 * @param addr The address to get the tag from.
251 * @return The tag of the address.
252 */
253 Addr extractTag(Addr addr) const override
254 {
255 return (addr >> tagShift);
256 }
257
258 /**
259 * Calculate the set index from the address.
260 * @param addr The address to get the set from.
261 * @return The set index of the address.
262 */
263 int extractSet(Addr addr) const override
264 {
265 return ((addr >> setShift) & setMask);
266 }
267
268 /**
269 * Regenerate the block address from the tag and set.
270 *
271 * @param block The block.
272 * @return the block address.
273 */
274 Addr regenerateBlkAddr(const CacheBlk* blk) const override
275 {
276 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
277 }
278
279 /**
280 * Called at end of simulation to complete average block reference stats.
281 */
282 void cleanupRefs() override;
283
284 /**
285 * Print all tags used
286 */
287 std::string print() const override;
288
289 /**
290 * Called prior to dumping stats to compute task occupancy
291 */
292 void computeStats() override;
293
294 /**
295 * Visit each block in the tag store and apply a visitor to the
296 * block.
297 *
298 * The visitor should be a function (or object that behaves like a
299 * function) that takes a cache block reference as its parameter
300 * and returns a bool. A visitor can request the traversal to be
301 * stopped by returning false, returning true causes it to be
302 * called for the next block in the tag store.
303 *
304 * \param visitor Visitor to call on each block.
305 */
306 void forEachBlk(CacheBlkVisitor &visitor) override {
307 for (CacheBlk& blk : blks) {
308 if (!visitor(blk))
309 return;
310 }
311 }
312};
313
314#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
| 248 }
249
250 /**
251 * Limit the allocation for the cache ways.
252 * @param ways The maximum number of ways available for replacement.
253 */
254 virtual void setWayAllocationMax(int ways) override
255 {
256 fatal_if(ways < 1, "Allocation limit must be greater than zero");
257 allocAssoc = ways;
258 }
259
260 /**
261 * Get the way allocation mask limit.
262 * @return The maximum number of ways available for replacement.
263 */
264 virtual int getWayAllocationMax() const override
265 {
266 return allocAssoc;
267 }
268
269 /**
270 * Generate the tag from the given address.
271 * @param addr The address to get the tag from.
272 * @return The tag of the address.
273 */
274 Addr extractTag(Addr addr) const override
275 {
276 return (addr >> tagShift);
277 }
278
279 /**
280 * Calculate the set index from the address.
281 * @param addr The address to get the set from.
282 * @return The set index of the address.
283 */
284 int extractSet(Addr addr) const override
285 {
286 return ((addr >> setShift) & setMask);
287 }
288
289 /**
290 * Regenerate the block address from the tag and set.
291 *
292 * @param block The block.
293 * @return the block address.
294 */
295 Addr regenerateBlkAddr(const CacheBlk* blk) const override
296 {
297 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
298 }
299
300 /**
301 * Called at end of simulation to complete average block reference stats.
302 */
303 void cleanupRefs() override;
304
305 /**
306 * Print all tags used
307 */
308 std::string print() const override;
309
310 /**
311 * Called prior to dumping stats to compute task occupancy
312 */
313 void computeStats() override;
314
315 /**
316 * Visit each block in the tag store and apply a visitor to the
317 * block.
318 *
319 * The visitor should be a function (or object that behaves like a
320 * function) that takes a cache block reference as its parameter
321 * and returns a bool. A visitor can request the traversal to be
322 * stopped by returning false, returning true causes it to be
323 * called for the next block in the tag store.
324 *
325 * \param visitor Visitor to call on each block.
326 */
327 void forEachBlk(CacheBlkVisitor &visitor) override {
328 for (CacheBlk& blk : blks) {
329 if (!visitor(blk))
330 return;
331 }
332 }
333};
334
335#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
|