base_set_assoc.hh (12600:e670dd17c8cf) base_set_assoc.hh (12629:c17d4dc2379e)
1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <cassert>
52#include <cstring>
53#include <memory>
54#include <vector>
55
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/tags/base.hh"
59#include "mem/cache/tags/cacheset.hh"
60#include "mem/packet.hh"
61#include "params/BaseSetAssoc.hh"
62
63/**
64 * A BaseSetAssoc cache tag store.
65 * @sa \ref gem5MemorySystem "gem5 Memory System"
66 *
67 * The BaseSetAssoc placement policy divides the cache into s sets of w
68 * cache lines (ways). A cache line is mapped onto a set, and can be placed
69 * into any of the ways of this set.
70 */
71class BaseSetAssoc : public BaseTags
72{
73 public:
74 /** Typedef the block type used in this tag store. */
75 typedef CacheBlk BlkType;
76 /** Typedef the set type used in this tag store. */
77 typedef CacheSet<CacheBlk> SetType;
78
1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <cassert>
52#include <cstring>
53#include <memory>
54#include <vector>
55
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/tags/base.hh"
59#include "mem/cache/tags/cacheset.hh"
60#include "mem/packet.hh"
61#include "params/BaseSetAssoc.hh"
62
63/**
64 * A BaseSetAssoc cache tag store.
65 * @sa \ref gem5MemorySystem "gem5 Memory System"
66 *
67 * The BaseSetAssoc placement policy divides the cache into s sets of w
68 * cache lines (ways). A cache line is mapped onto a set, and can be placed
69 * into any of the ways of this set.
70 */
71class BaseSetAssoc : public BaseTags
72{
73 public:
74 /** Typedef the block type used in this tag store. */
75 typedef CacheBlk BlkType;
76 /** Typedef the set type used in this tag store. */
77 typedef CacheSet<CacheBlk> SetType;
78
79
80 protected:
81 /** The associativity of the cache. */
82 const unsigned assoc;
83 /** The allocatable associativity of the cache (alloc mask). */
84 unsigned allocAssoc;
85
86 /** The cache blocks. */
87 std::vector<BlkType> blks;
79 protected:
80 /** The associativity of the cache. */
81 const unsigned assoc;
82 /** The allocatable associativity of the cache (alloc mask). */
83 unsigned allocAssoc;
84
85 /** The cache blocks. */
86 std::vector<BlkType> blks;
88 /** The data blocks, 1 per cache block. */
89 std::unique_ptr<uint8_t[]> dataBlks;
90
91 /** The number of sets in the cache. */
92 const unsigned numSets;
93
94 /** Whether tags and data are accessed sequentially. */
95 const bool sequentialAccess;
96
97 /** The cache sets. */
98 std::vector<SetType> sets;
99
100 /** The amount to shift the address to get the set. */
101 int setShift;
102 /** The amount to shift the address to get the tag. */
103 int tagShift;
104 /** Mask out all bits that aren't part of the set index. */
105 unsigned setMask;
106
107 /** Replacement policy */
108 BaseReplacementPolicy *replacementPolicy;
109
110 public:
111
112 /** Convenience typedef. */
113 typedef BaseSetAssocParams Params;
114
115 /**
116 * Construct and initialize this tag store.
117 */
118 BaseSetAssoc(const Params *p);
119
120 /**
121 * Destructor
122 */
123 virtual ~BaseSetAssoc() {};
124
125 /**
126 * Find the cache block given set and way
127 * @param set The set of the block.
128 * @param way The way of the block.
129 * @return The cache block.
130 */
131 CacheBlk *findBlockBySetAndWay(int set, int way) const override;
132
133 /**
134 * Access block and update replacement data. May not succeed, in which case
135 * nullptr is returned. This has all the implications of a cache
136 * access and should only be used as such. Returns the access latency as a
137 * side effect.
138 * @param addr The address to find.
139 * @param is_secure True if the target memory space is secure.
140 * @param lat The access latency.
141 * @return Pointer to the cache block if found.
142 */
143 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
144 {
145 BlkType *blk = findBlock(addr, is_secure);
146
147 // Access all tags in parallel, hence one in each way. The data side
148 // either accesses all blocks in parallel, or one block sequentially on
149 // a hit. Sequential access with a miss doesn't access data.
150 tagAccesses += allocAssoc;
151 if (sequentialAccess) {
152 if (blk != nullptr) {
153 dataAccesses += 1;
154 }
155 } else {
156 dataAccesses += allocAssoc;
157 }
158
159 if (blk != nullptr) {
160 // If a cache hit
161 lat = accessLatency;
162 // Check if the block to be accessed is available. If not,
163 // apply the accessLatency on top of block->whenReady.
164 if (blk->whenReady > curTick() &&
165 cache->ticksToCycles(blk->whenReady - curTick()) >
166 accessLatency) {
167 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
168 accessLatency;
169 }
170
171 // Update replacement data of accessed block
172 replacementPolicy->touch(blk);
173 } else {
174 // If a cache miss
175 lat = lookupLatency;
176 }
177
178 return blk;
179 }
180
181 /**
182 * Finds the given address in the cache, do not update replacement data.
183 * i.e. This is a no-side-effect find of a block.
184 * @param addr The address to find.
185 * @param is_secure True if the target memory space is secure.
186 * @param asid The address space ID.
187 * @return Pointer to the cache block if found.
188 */
189 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
190
191 /**
192 * Find replacement victim based on address.
193 *
194 * @param addr Address to find a victim for.
195 * @return Cache block to be replaced.
196 */
197 CacheBlk* findVictim(Addr addr) override
198 {
199 // Choose replacement victim from replacement candidates
200 return replacementPolicy->getVictim(getPossibleLocations(addr));
201 }
202
203 /**
204 * Find all possible block locations for insertion and replacement of
205 * an address. Should be called immediately before ReplacementPolicy's
206 * findVictim() not to break cache resizing.
207 * Returns blocks in all ways belonging to the set of the address.
208 *
209 * @param addr The addr to a find possible locations for.
210 * @return The possible locations.
211 */
212 const std::vector<CacheBlk*> getPossibleLocations(Addr addr)
213 {
214 return sets[extractSet(addr)].blks;
215 }
216
217 /**
218 * Insert the new block into the cache.
219 * @param pkt Packet holding the address to update
220 * @param blk The block to update.
221 */
222 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
223 {
224 Addr addr = pkt->getAddr();
225 MasterID master_id = pkt->req->masterId();
226 uint32_t task_id = pkt->req->taskId();
227
228 if (!blk->isTouched) {
229 if (!warmedUp && tagsInUse.value() >= warmupBound) {
230 warmedUp = true;
231 warmupCycle = curTick();
232 }
233 }
234
235 // If we're replacing a block that was previously valid update
236 // stats for it. This can't be done in findBlock() because a
237 // found block might not actually be replaced there if the
238 // coherence protocol says it can't be.
239 if (blk->isValid()) {
240 replacements[0]++;
241 totalRefs += blk->refCount;
242 ++sampledRefs;
243
244 invalidate(blk);
245 blk->invalidate();
246 }
247
248 // Previous block, if existed, has been removed, and now we have
249 // to insert the new one
250 tagsInUse++;
251
252 // Set tag for new block. Caller is responsible for setting status.
253 blk->tag = extractTag(addr);
254
255 // deal with what we are bringing in
256 assert(master_id < cache->system->maxMasters());
257 occupancies[master_id]++;
258 blk->srcMasterId = master_id;
259 blk->task_id = task_id;
260
261 // We only need to write into one tag and one data block.
262 tagAccesses += 1;
263 dataAccesses += 1;
264
265 replacementPolicy->reset(blk);
266 }
267
268 /**
269 * Limit the allocation for the cache ways.
270 * @param ways The maximum number of ways available for replacement.
271 */
272 virtual void setWayAllocationMax(int ways) override
273 {
274 fatal_if(ways < 1, "Allocation limit must be greater than zero");
275 allocAssoc = ways;
276 }
277
278 /**
279 * Get the way allocation mask limit.
280 * @return The maximum number of ways available for replacement.
281 */
282 virtual int getWayAllocationMax() const override
283 {
284 return allocAssoc;
285 }
286
287 /**
288 * Generate the tag from the given address.
289 * @param addr The address to get the tag from.
290 * @return The tag of the address.
291 */
292 Addr extractTag(Addr addr) const override
293 {
294 return (addr >> tagShift);
295 }
296
297 /**
298 * Calculate the set index from the address.
299 * @param addr The address to get the set from.
300 * @return The set index of the address.
301 */
302 int extractSet(Addr addr) const override
303 {
304 return ((addr >> setShift) & setMask);
305 }
306
307 /**
308 * Regenerate the block address from the tag and set.
309 *
310 * @param block The block.
311 * @return the block address.
312 */
313 Addr regenerateBlkAddr(const CacheBlk* blk) const override
314 {
315 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
316 }
317
318 /**
319 * Called at end of simulation to complete average block reference stats.
320 */
321 void cleanupRefs() override;
322
323 /**
324 * Print all tags used
325 */
326 std::string print() const override;
327
328 /**
329 * Called prior to dumping stats to compute task occupancy
330 */
331 void computeStats() override;
332
333 /**
334 * Visit each block in the tag store and apply a visitor to the
335 * block.
336 *
337 * The visitor should be a function (or object that behaves like a
338 * function) that takes a cache block reference as its parameter
339 * and returns a bool. A visitor can request the traversal to be
340 * stopped by returning false, returning true causes it to be
341 * called for the next block in the tag store.
342 *
343 * \param visitor Visitor to call on each block.
344 */
345 void forEachBlk(CacheBlkVisitor &visitor) override {
346 for (unsigned i = 0; i < numSets * assoc; ++i) {
347 if (!visitor(blks[i]))
348 return;
349 }
350 }
351};
352
353#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
87
88 /** The number of sets in the cache. */
89 const unsigned numSets;
90
91 /** Whether tags and data are accessed sequentially. */
92 const bool sequentialAccess;
93
94 /** The cache sets. */
95 std::vector<SetType> sets;
96
97 /** The amount to shift the address to get the set. */
98 int setShift;
99 /** The amount to shift the address to get the tag. */
100 int tagShift;
101 /** Mask out all bits that aren't part of the set index. */
102 unsigned setMask;
103
104 /** Replacement policy */
105 BaseReplacementPolicy *replacementPolicy;
106
107 public:
108
109 /** Convenience typedef. */
110 typedef BaseSetAssocParams Params;
111
112 /**
113 * Construct and initialize this tag store.
114 */
115 BaseSetAssoc(const Params *p);
116
117 /**
118 * Destructor
119 */
120 virtual ~BaseSetAssoc() {};
121
122 /**
123 * Find the cache block given set and way
124 * @param set The set of the block.
125 * @param way The way of the block.
126 * @return The cache block.
127 */
128 CacheBlk *findBlockBySetAndWay(int set, int way) const override;
129
130 /**
131 * Access block and update replacement data. May not succeed, in which case
132 * nullptr is returned. This has all the implications of a cache
133 * access and should only be used as such. Returns the access latency as a
134 * side effect.
135 * @param addr The address to find.
136 * @param is_secure True if the target memory space is secure.
137 * @param lat The access latency.
138 * @return Pointer to the cache block if found.
139 */
140 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
141 {
142 BlkType *blk = findBlock(addr, is_secure);
143
144 // Access all tags in parallel, hence one in each way. The data side
145 // either accesses all blocks in parallel, or one block sequentially on
146 // a hit. Sequential access with a miss doesn't access data.
147 tagAccesses += allocAssoc;
148 if (sequentialAccess) {
149 if (blk != nullptr) {
150 dataAccesses += 1;
151 }
152 } else {
153 dataAccesses += allocAssoc;
154 }
155
156 if (blk != nullptr) {
157 // If a cache hit
158 lat = accessLatency;
159 // Check if the block to be accessed is available. If not,
160 // apply the accessLatency on top of block->whenReady.
161 if (blk->whenReady > curTick() &&
162 cache->ticksToCycles(blk->whenReady - curTick()) >
163 accessLatency) {
164 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
165 accessLatency;
166 }
167
168 // Update replacement data of accessed block
169 replacementPolicy->touch(blk);
170 } else {
171 // If a cache miss
172 lat = lookupLatency;
173 }
174
175 return blk;
176 }
177
178 /**
179 * Finds the given address in the cache, do not update replacement data.
180 * i.e. This is a no-side-effect find of a block.
181 * @param addr The address to find.
182 * @param is_secure True if the target memory space is secure.
183 * @param asid The address space ID.
184 * @return Pointer to the cache block if found.
185 */
186 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
187
188 /**
189 * Find replacement victim based on address.
190 *
191 * @param addr Address to find a victim for.
192 * @return Cache block to be replaced.
193 */
194 CacheBlk* findVictim(Addr addr) override
195 {
196 // Choose replacement victim from replacement candidates
197 return replacementPolicy->getVictim(getPossibleLocations(addr));
198 }
199
200 /**
201 * Find all possible block locations for insertion and replacement of
202 * an address. Should be called immediately before ReplacementPolicy's
203 * findVictim() not to break cache resizing.
204 * Returns blocks in all ways belonging to the set of the address.
205 *
206 * @param addr The addr to a find possible locations for.
207 * @return The possible locations.
208 */
209 const std::vector<CacheBlk*> getPossibleLocations(Addr addr)
210 {
211 return sets[extractSet(addr)].blks;
212 }
213
214 /**
215 * Insert the new block into the cache.
216 * @param pkt Packet holding the address to update
217 * @param blk The block to update.
218 */
219 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
220 {
221 Addr addr = pkt->getAddr();
222 MasterID master_id = pkt->req->masterId();
223 uint32_t task_id = pkt->req->taskId();
224
225 if (!blk->isTouched) {
226 if (!warmedUp && tagsInUse.value() >= warmupBound) {
227 warmedUp = true;
228 warmupCycle = curTick();
229 }
230 }
231
232 // If we're replacing a block that was previously valid update
233 // stats for it. This can't be done in findBlock() because a
234 // found block might not actually be replaced there if the
235 // coherence protocol says it can't be.
236 if (blk->isValid()) {
237 replacements[0]++;
238 totalRefs += blk->refCount;
239 ++sampledRefs;
240
241 invalidate(blk);
242 blk->invalidate();
243 }
244
245 // Previous block, if existed, has been removed, and now we have
246 // to insert the new one
247 tagsInUse++;
248
249 // Set tag for new block. Caller is responsible for setting status.
250 blk->tag = extractTag(addr);
251
252 // deal with what we are bringing in
253 assert(master_id < cache->system->maxMasters());
254 occupancies[master_id]++;
255 blk->srcMasterId = master_id;
256 blk->task_id = task_id;
257
258 // We only need to write into one tag and one data block.
259 tagAccesses += 1;
260 dataAccesses += 1;
261
262 replacementPolicy->reset(blk);
263 }
264
265 /**
266 * Limit the allocation for the cache ways.
267 * @param ways The maximum number of ways available for replacement.
268 */
269 virtual void setWayAllocationMax(int ways) override
270 {
271 fatal_if(ways < 1, "Allocation limit must be greater than zero");
272 allocAssoc = ways;
273 }
274
275 /**
276 * Get the way allocation mask limit.
277 * @return The maximum number of ways available for replacement.
278 */
279 virtual int getWayAllocationMax() const override
280 {
281 return allocAssoc;
282 }
283
284 /**
285 * Generate the tag from the given address.
286 * @param addr The address to get the tag from.
287 * @return The tag of the address.
288 */
289 Addr extractTag(Addr addr) const override
290 {
291 return (addr >> tagShift);
292 }
293
294 /**
295 * Calculate the set index from the address.
296 * @param addr The address to get the set from.
297 * @return The set index of the address.
298 */
299 int extractSet(Addr addr) const override
300 {
301 return ((addr >> setShift) & setMask);
302 }
303
304 /**
305 * Regenerate the block address from the tag and set.
306 *
307 * @param block The block.
308 * @return the block address.
309 */
310 Addr regenerateBlkAddr(const CacheBlk* blk) const override
311 {
312 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
313 }
314
315 /**
316 * Called at end of simulation to complete average block reference stats.
317 */
318 void cleanupRefs() override;
319
320 /**
321 * Print all tags used
322 */
323 std::string print() const override;
324
325 /**
326 * Called prior to dumping stats to compute task occupancy
327 */
328 void computeStats() override;
329
330 /**
331 * Visit each block in the tag store and apply a visitor to the
332 * block.
333 *
334 * The visitor should be a function (or object that behaves like a
335 * function) that takes a cache block reference as its parameter
336 * and returns a bool. A visitor can request the traversal to be
337 * stopped by returning false, returning true causes it to be
338 * called for the next block in the tag store.
339 *
340 * \param visitor Visitor to call on each block.
341 */
342 void forEachBlk(CacheBlkVisitor &visitor) override {
343 for (unsigned i = 0; i < numSets * assoc; ++i) {
344 if (!visitor(blks[i]))
345 return;
346 }
347 }
348};
349
350#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__