1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <cassert>
52#include <cstring>
53#include <memory>
54#include <vector>
55
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/tags/base.hh"
59#include "mem/cache/tags/cacheset.hh"
60#include "mem/packet.hh"
61#include "params/BaseSetAssoc.hh"
62
63/**
64 * A BaseSetAssoc cache tag store.
65 * @sa \ref gem5MemorySystem "gem5 Memory System"
66 *
| 1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <cassert>
52#include <cstring>
53#include <memory>
54#include <vector>
55
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/tags/base.hh"
59#include "mem/cache/tags/cacheset.hh"
60#include "mem/packet.hh"
61#include "params/BaseSetAssoc.hh"
62
63/**
64 * A BaseSetAssoc cache tag store.
65 * @sa \ref gem5MemorySystem "gem5 Memory System"
66 *
|
67 * The BaseSetAssoc tags provide a base, as well as the functionality
68 * common to any set associative tags. Any derived class must implement
69 * the methods related to the specifics of the actual replacment policy.
70 * These are:
71 *
72 * BlkType* accessBlock();
73 * BlkType* findVictim();
74 * void insertBlock();
| 67 * The BaseSetAssoc placement policy divides the cache into s sets of w
68 * cache lines (ways). A cache line is mapped onto a set, and can be placed
69 * into any of the ways of this set.
|
75 */
76class BaseSetAssoc : public BaseTags
77{
78 public:
79 /** Typedef the block type used in this tag store. */
80 typedef CacheBlk BlkType;
81 /** Typedef the set type used in this tag store. */
82 typedef CacheSet<CacheBlk> SetType;
83
84
85 protected:
86 /** The associativity of the cache. */
87 const unsigned assoc;
88 /** The allocatable associativity of the cache (alloc mask). */
89 unsigned allocAssoc;
90
91 /** The cache blocks. */
92 std::vector<BlkType> blks;
93 /** The data blocks, 1 per cache block. */
94 std::unique_ptr<uint8_t[]> dataBlks;
95
96 /** The number of sets in the cache. */
97 const unsigned numSets;
98
99 /** Whether tags and data are accessed sequentially. */
100 const bool sequentialAccess;
101
102 /** The cache sets. */
103 std::vector<SetType> sets;
104
105 /** The amount to shift the address to get the set. */
106 int setShift;
107 /** The amount to shift the address to get the tag. */
108 int tagShift;
109 /** Mask out all bits that aren't part of the set index. */
110 unsigned setMask;
111
| 70 */
71class BaseSetAssoc : public BaseTags
72{
73 public:
74 /** Typedef the block type used in this tag store. */
75 typedef CacheBlk BlkType;
76 /** Typedef the set type used in this tag store. */
77 typedef CacheSet<CacheBlk> SetType;
78
79
80 protected:
81 /** The associativity of the cache. */
82 const unsigned assoc;
83 /** The allocatable associativity of the cache (alloc mask). */
84 unsigned allocAssoc;
85
86 /** The cache blocks. */
87 std::vector<BlkType> blks;
88 /** The data blocks, 1 per cache block. */
89 std::unique_ptr<uint8_t[]> dataBlks;
90
91 /** The number of sets in the cache. */
92 const unsigned numSets;
93
94 /** Whether tags and data are accessed sequentially. */
95 const bool sequentialAccess;
96
97 /** The cache sets. */
98 std::vector<SetType> sets;
99
100 /** The amount to shift the address to get the set. */
101 int setShift;
102 /** The amount to shift the address to get the tag. */
103 int tagShift;
104 /** Mask out all bits that aren't part of the set index. */
105 unsigned setMask;
106
|
112public:
| 107 /** Replacement policy */
108 BaseReplacementPolicy *replacementPolicy;
|
113
| 109
|
| 110 public:
111
|
114 /** Convenience typedef. */
115 typedef BaseSetAssocParams Params;
116
117 /**
118 * Construct and initialize this tag store.
119 */
120 BaseSetAssoc(const Params *p);
121
122 /**
123 * Destructor
124 */
125 virtual ~BaseSetAssoc() {};
126
127 /**
128 * Find the cache block given set and way
129 * @param set The set of the block.
130 * @param way The way of the block.
131 * @return The cache block.
132 */
133 CacheBlk *findBlockBySetAndWay(int set, int way) const override;
134
135 /**
136 * Access block and update replacement data. May not succeed, in which case
137 * nullptr is returned. This has all the implications of a cache
138 * access and should only be used as such. Returns the access latency as a
139 * side effect.
140 * @param addr The address to find.
141 * @param is_secure True if the target memory space is secure.
142 * @param lat The access latency.
143 * @return Pointer to the cache block if found.
144 */
145 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
146 {
147 BlkType *blk = findBlock(addr, is_secure);
148
149 // Access all tags in parallel, hence one in each way. The data side
150 // either accesses all blocks in parallel, or one block sequentially on
151 // a hit. Sequential access with a miss doesn't access data.
152 tagAccesses += allocAssoc;
153 if (sequentialAccess) {
154 if (blk != nullptr) {
155 dataAccesses += 1;
156 }
157 } else {
158 dataAccesses += allocAssoc;
159 }
160
161 if (blk != nullptr) {
162 // If a cache hit
163 lat = accessLatency;
164 // Check if the block to be accessed is available. If not,
165 // apply the accessLatency on top of block->whenReady.
166 if (blk->whenReady > curTick() &&
167 cache->ticksToCycles(blk->whenReady - curTick()) >
168 accessLatency) {
169 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
170 accessLatency;
171 }
| 112 /** Convenience typedef. */
113 typedef BaseSetAssocParams Params;
114
115 /**
116 * Construct and initialize this tag store.
117 */
118 BaseSetAssoc(const Params *p);
119
120 /**
121 * Destructor
122 */
123 virtual ~BaseSetAssoc() {};
124
125 /**
126 * Find the cache block given set and way
127 * @param set The set of the block.
128 * @param way The way of the block.
129 * @return The cache block.
130 */
131 CacheBlk *findBlockBySetAndWay(int set, int way) const override;
132
133 /**
134 * Access block and update replacement data. May not succeed, in which case
135 * nullptr is returned. This has all the implications of a cache
136 * access and should only be used as such. Returns the access latency as a
137 * side effect.
138 * @param addr The address to find.
139 * @param is_secure True if the target memory space is secure.
140 * @param lat The access latency.
141 * @return Pointer to the cache block if found.
142 */
143 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
144 {
145 BlkType *blk = findBlock(addr, is_secure);
146
147 // Access all tags in parallel, hence one in each way. The data side
148 // either accesses all blocks in parallel, or one block sequentially on
149 // a hit. Sequential access with a miss doesn't access data.
150 tagAccesses += allocAssoc;
151 if (sequentialAccess) {
152 if (blk != nullptr) {
153 dataAccesses += 1;
154 }
155 } else {
156 dataAccesses += allocAssoc;
157 }
158
159 if (blk != nullptr) {
160 // If a cache hit
161 lat = accessLatency;
162 // Check if the block to be accessed is available. If not,
163 // apply the accessLatency on top of block->whenReady.
164 if (blk->whenReady > curTick() &&
165 cache->ticksToCycles(blk->whenReady - curTick()) >
166 accessLatency) {
167 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
168 accessLatency;
169 }
|
172 blk->refCount += 1;
| 170
171 // Update replacement data of accessed block
172 replacementPolicy->touch(blk);
|
173 } else {
174 // If a cache miss
175 lat = lookupLatency;
176 }
177
178 return blk;
179 }
180
181 /**
182 * Finds the given address in the cache, do not update replacement data.
183 * i.e. This is a no-side-effect find of a block.
184 * @param addr The address to find.
185 * @param is_secure True if the target memory space is secure.
186 * @param asid The address space ID.
187 * @return Pointer to the cache block if found.
188 */
189 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
190
191 /**
| 173 } else {
174 // If a cache miss
175 lat = lookupLatency;
176 }
177
178 return blk;
179 }
180
181 /**
182 * Finds the given address in the cache, do not update replacement data.
183 * i.e. This is a no-side-effect find of a block.
184 * @param addr The address to find.
185 * @param is_secure True if the target memory space is secure.
186 * @param asid The address space ID.
187 * @return Pointer to the cache block if found.
188 */
189 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
190
191 /**
|
192 * Find an invalid block to evict for the address provided.
193 * If there are no invalid blocks, this will return the block
194 * in the least-recently-used position.
195 * @param addr The addr to a find a replacement candidate for.
196 * @return The candidate block.
| 192 * Find replacement victim based on address.
193 *
194 * @param addr Address to find a victim for.
195 * @return Cache block to be replaced.
|
197 */
198 CacheBlk* findVictim(Addr addr) override
199 {
| 196 */
197 CacheBlk* findVictim(Addr addr) override
198 {
|
200 BlkType *blk = nullptr;
201 int set = extractSet(addr);
| 199 // Choose replacement victim from replacement candidates
200 return replacementPolicy->getVictim(getPossibleLocations(addr));
201 }
|
202
| 202
|
203 // prefer to evict an invalid block
204 for (int i = 0; i < allocAssoc; ++i) {
205 blk = sets[set].blks[i];
206 if (!blk->isValid())
207 break;
208 }
209
210 return blk;
| 203 /**
204 * Find all possible block locations for insertion and replacement of
205 * an address. Should be called immediately before ReplacementPolicy's
206 * findVictim() not to break cache resizing.
207 * Returns blocks in all ways belonging to the set of the address.
208 *
209 * @param addr The addr to a find possible locations for.
210 * @return The possible locations.
211 */
212 const std::vector<CacheBlk*> getPossibleLocations(Addr addr)
213 {
214 return sets[extractSet(addr)].blks;
|
211 }
212
213 /**
214 * Insert the new block into the cache.
215 * @param pkt Packet holding the address to update
216 * @param blk The block to update.
217 */
218 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
219 {
220 Addr addr = pkt->getAddr();
221 MasterID master_id = pkt->req->masterId();
222 uint32_t task_id = pkt->req->taskId();
223
224 if (!blk->isTouched) {
225 if (!warmedUp && tagsInUse.value() >= warmupBound) {
226 warmedUp = true;
227 warmupCycle = curTick();
228 }
229 }
230
231 // If we're replacing a block that was previously valid update
232 // stats for it. This can't be done in findBlock() because a
233 // found block might not actually be replaced there if the
234 // coherence protocol says it can't be.
235 if (blk->isValid()) {
236 replacements[0]++;
237 totalRefs += blk->refCount;
238 ++sampledRefs;
239
240 invalidate(blk);
241 blk->invalidate();
242 }
243
244 // Previous block, if existed, has been removed, and now we have
| 215 }
216
217 /**
218 * Insert the new block into the cache.
219 * @param pkt Packet holding the address to update
220 * @param blk The block to update.
221 */
222 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
223 {
224 Addr addr = pkt->getAddr();
225 MasterID master_id = pkt->req->masterId();
226 uint32_t task_id = pkt->req->taskId();
227
228 if (!blk->isTouched) {
229 if (!warmedUp && tagsInUse.value() >= warmupBound) {
230 warmedUp = true;
231 warmupCycle = curTick();
232 }
233 }
234
235 // If we're replacing a block that was previously valid update
236 // stats for it. This can't be done in findBlock() because a
237 // found block might not actually be replaced there if the
238 // coherence protocol says it can't be.
239 if (blk->isValid()) {
240 replacements[0]++;
241 totalRefs += blk->refCount;
242 ++sampledRefs;
243
244 invalidate(blk);
245 blk->invalidate();
246 }
247
248 // Previous block, if existed, has been removed, and now we have
|
245 // to insert the new one and mark it as touched
| 249 // to insert the new one
|
246 tagsInUse++;
| 250 tagsInUse++;
|
247 blk->isTouched = true;
| |
248
249 // Set tag for new block. Caller is responsible for setting status.
250 blk->tag = extractTag(addr);
251
252 // deal with what we are bringing in
253 assert(master_id < cache->system->maxMasters());
254 occupancies[master_id]++;
255 blk->srcMasterId = master_id;
256 blk->task_id = task_id;
| 251
252 // Set tag for new block. Caller is responsible for setting status.
253 blk->tag = extractTag(addr);
254
255 // deal with what we are bringing in
256 assert(master_id < cache->system->maxMasters());
257 occupancies[master_id]++;
258 blk->srcMasterId = master_id;
259 blk->task_id = task_id;
|
257 blk->tickInserted = curTick();
| |
258
259 // We only need to write into one tag and one data block.
260 tagAccesses += 1;
261 dataAccesses += 1;
| 260
261 // We only need to write into one tag and one data block.
262 tagAccesses += 1;
263 dataAccesses += 1;
|
| 264
265 replacementPolicy->reset(blk);
|
262 }
263
264 /**
265 * Limit the allocation for the cache ways.
266 * @param ways The maximum number of ways available for replacement.
267 */
268 virtual void setWayAllocationMax(int ways) override
269 {
270 fatal_if(ways < 1, "Allocation limit must be greater than zero");
271 allocAssoc = ways;
272 }
273
274 /**
275 * Get the way allocation mask limit.
276 * @return The maximum number of ways available for replacement.
277 */
278 virtual int getWayAllocationMax() const override
279 {
280 return allocAssoc;
281 }
282
283 /**
284 * Generate the tag from the given address.
285 * @param addr The address to get the tag from.
286 * @return The tag of the address.
287 */
288 Addr extractTag(Addr addr) const override
289 {
290 return (addr >> tagShift);
291 }
292
293 /**
294 * Calculate the set index from the address.
295 * @param addr The address to get the set from.
296 * @return The set index of the address.
297 */
298 int extractSet(Addr addr) const override
299 {
300 return ((addr >> setShift) & setMask);
301 }
302
303 /**
304 * Regenerate the block address from the tag and set.
305 *
306 * @param block The block.
307 * @return the block address.
308 */
309 Addr regenerateBlkAddr(const CacheBlk* blk) const override
310 {
311 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
312 }
313
314 /**
315 * Called at end of simulation to complete average block reference stats.
316 */
317 void cleanupRefs() override;
318
319 /**
320 * Print all tags used
321 */
322 std::string print() const override;
323
324 /**
325 * Called prior to dumping stats to compute task occupancy
326 */
327 void computeStats() override;
328
329 /**
330 * Visit each block in the tag store and apply a visitor to the
331 * block.
332 *
333 * The visitor should be a function (or object that behaves like a
334 * function) that takes a cache block reference as its parameter
335 * and returns a bool. A visitor can request the traversal to be
336 * stopped by returning false, returning true causes it to be
337 * called for the next block in the tag store.
338 *
339 * \param visitor Visitor to call on each block.
340 */
341 void forEachBlk(CacheBlkVisitor &visitor) override {
342 for (unsigned i = 0; i < numSets * assoc; ++i) {
343 if (!visitor(blks[i]))
344 return;
345 }
346 }
347};
348
349#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
| 266 }
267
268 /**
269 * Limit the allocation for the cache ways.
270 * @param ways The maximum number of ways available for replacement.
271 */
272 virtual void setWayAllocationMax(int ways) override
273 {
274 fatal_if(ways < 1, "Allocation limit must be greater than zero");
275 allocAssoc = ways;
276 }
277
278 /**
279 * Get the way allocation mask limit.
280 * @return The maximum number of ways available for replacement.
281 */
282 virtual int getWayAllocationMax() const override
283 {
284 return allocAssoc;
285 }
286
287 /**
288 * Generate the tag from the given address.
289 * @param addr The address to get the tag from.
290 * @return The tag of the address.
291 */
292 Addr extractTag(Addr addr) const override
293 {
294 return (addr >> tagShift);
295 }
296
297 /**
298 * Calculate the set index from the address.
299 * @param addr The address to get the set from.
300 * @return The set index of the address.
301 */
302 int extractSet(Addr addr) const override
303 {
304 return ((addr >> setShift) & setMask);
305 }
306
307 /**
308 * Regenerate the block address from the tag and set.
309 *
310 * @param block The block.
311 * @return the block address.
312 */
313 Addr regenerateBlkAddr(const CacheBlk* blk) const override
314 {
315 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift));
316 }
317
318 /**
319 * Called at end of simulation to complete average block reference stats.
320 */
321 void cleanupRefs() override;
322
323 /**
324 * Print all tags used
325 */
326 std::string print() const override;
327
328 /**
329 * Called prior to dumping stats to compute task occupancy
330 */
331 void computeStats() override;
332
333 /**
334 * Visit each block in the tag store and apply a visitor to the
335 * block.
336 *
337 * The visitor should be a function (or object that behaves like a
338 * function) that takes a cache block reference as its parameter
339 * and returns a bool. A visitor can request the traversal to be
340 * stopped by returning false, returning true causes it to be
341 * called for the next block in the tag store.
342 *
343 * \param visitor Visitor to call on each block.
344 */
345 void forEachBlk(CacheBlkVisitor &visitor) override {
346 for (unsigned i = 0; i < numSets * assoc; ++i) {
347 if (!visitor(blks[i]))
348 return;
349 }
350 }
351};
352
353#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
|