1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 50 51#include <cassert> 52#include <cstring> 53#include <memory> 54#include <vector> 55 56#include "mem/cache/base.hh" 57#include "mem/cache/blk.hh" 58#include "mem/cache/tags/base.hh" 59#include "mem/cache/tags/cacheset.hh" 60#include "mem/packet.hh" 61#include "params/BaseSetAssoc.hh" 62 63/** 64 * A BaseSetAssoc cache tag store. 65 * @sa \ref gem5MemorySystem "gem5 Memory System" 66 * 67 * The BaseSetAssoc tags provide a base, as well as the functionality 68 * common to any set associative tags. Any derived class must implement 69 * the methods related to the specifics of the actual replacment policy. 70 * These are: 71 * 72 * BlkType* accessBlock(); 73 * BlkType* findVictim(); 74 * void insertBlock(); 75 * void invalidate(); 76 */ 77class BaseSetAssoc : public BaseTags 78{ 79 public: 80 /** Typedef the block type used in this tag store. */ 81 typedef CacheBlk BlkType; 82 /** Typedef the set type used in this tag store. */ 83 typedef CacheSet<CacheBlk> SetType; 84 85 86 protected: 87 /** The associativity of the cache. */ 88 const unsigned assoc; 89 /** The allocatable associativity of the cache (alloc mask). */ 90 unsigned allocAssoc; 91 92 /** The cache blocks. */ 93 std::vector<BlkType> blks; 94 /** The data blocks, 1 per cache block. */ 95 std::unique_ptr<uint8_t[]> dataBlks; 96 97 /** The number of sets in the cache. */ 98 const unsigned numSets; 99 100 /** Whether tags and data are accessed sequentially. */ 101 const bool sequentialAccess; 102 103 /** The cache sets. */ 104 std::vector<SetType> sets; 105 106 /** The amount to shift the address to get the set. */ 107 int setShift; 108 /** The amount to shift the address to get the tag. */ 109 int tagShift; 110 /** Mask out all bits that aren't part of the set index. */ 111 unsigned setMask; 112 113public: 114 115 /** Convenience typedef. */ 116 typedef BaseSetAssocParams Params; 117 118 /** 119 * Construct and initialize this tag store. 120 */ 121 BaseSetAssoc(const Params *p); 122 123 /** 124 * Destructor 125 */ 126 virtual ~BaseSetAssoc() {}; 127 128 /** 129 * Find the cache block given set and way 130 * @param set The set of the block. 131 * @param way The way of the block. 132 * @return The cache block. 133 */ 134 CacheBlk *findBlockBySetAndWay(int set, int way) const override; 135 136 /** 137 * Invalidate the given block. 138 * @param blk The block to invalidate. 139 */ 140 void invalidate(CacheBlk *blk) override 141 { 142 assert(blk); 143 assert(blk->isValid()); 144 tagsInUse--; 145 assert(blk->srcMasterId < cache->system->maxMasters()); 146 occupancies[blk->srcMasterId]--; 147 blk->srcMasterId = Request::invldMasterId; 148 blk->task_id = ContextSwitchTaskId::Unknown; 149 blk->tickInserted = curTick(); 150 } 151 152 /** 153 * Access block and update replacement data. May not succeed, in which case 154 * nullptr is returned. This has all the implications of a cache 155 * access and should only be used as such. Returns the access latency as a 156 * side effect. 157 * @param addr The address to find. 158 * @param is_secure True if the target memory space is secure. 159 * @param lat The access latency. 160 * @return Pointer to the cache block if found. 161 */ 162 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 163 { 164 BlkType *blk = findBlock(addr, is_secure); 165 166 // Access all tags in parallel, hence one in each way. The data side 167 // either accesses all blocks in parallel, or one block sequentially on 168 // a hit. Sequential access with a miss doesn't access data. 169 tagAccesses += allocAssoc; 170 if (sequentialAccess) { 171 if (blk != nullptr) { 172 dataAccesses += 1; 173 } 174 } else { 175 dataAccesses += allocAssoc; 176 } 177 178 if (blk != nullptr) { 179 // If a cache hit 180 lat = accessLatency; 181 // Check if the block to be accessed is available. If not, 182 // apply the accessLatency on top of block->whenReady. 183 if (blk->whenReady > curTick() && 184 cache->ticksToCycles(blk->whenReady - curTick()) > 185 accessLatency) { 186 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 187 accessLatency; 188 } 189 blk->refCount += 1; 190 } else { 191 // If a cache miss 192 lat = lookupLatency; 193 } 194 195 return blk; 196 } 197 198 /** 199 * Finds the given address in the cache, do not update replacement data. 200 * i.e. This is a no-side-effect find of a block. 201 * @param addr The address to find. 202 * @param is_secure True if the target memory space is secure. 203 * @param asid The address space ID. 204 * @return Pointer to the cache block if found. 205 */ 206 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 207 208 /** 209 * Find an invalid block to evict for the address provided. 210 * If there are no invalid blocks, this will return the block 211 * in the least-recently-used position. 212 * @param addr The addr to a find a replacement candidate for. 213 * @return The candidate block. 214 */ 215 CacheBlk* findVictim(Addr addr) override 216 { 217 BlkType *blk = nullptr; 218 int set = extractSet(addr); 219 220 // prefer to evict an invalid block 221 for (int i = 0; i < allocAssoc; ++i) { 222 blk = sets[set].blks[i]; 223 if (!blk->isValid()) 224 break; 225 } 226 227 return blk; 228 } 229 230 /** 231 * Insert the new block into the cache. 232 * @param pkt Packet holding the address to update 233 * @param blk The block to update. 234 */ 235 void insertBlock(PacketPtr pkt, CacheBlk *blk) override 236 { 237 Addr addr = pkt->getAddr(); 238 MasterID master_id = pkt->req->masterId(); 239 uint32_t task_id = pkt->req->taskId(); 240 241 if (!blk->isTouched) {
| 1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 50 51#include <cassert> 52#include <cstring> 53#include <memory> 54#include <vector> 55 56#include "mem/cache/base.hh" 57#include "mem/cache/blk.hh" 58#include "mem/cache/tags/base.hh" 59#include "mem/cache/tags/cacheset.hh" 60#include "mem/packet.hh" 61#include "params/BaseSetAssoc.hh" 62 63/** 64 * A BaseSetAssoc cache tag store. 65 * @sa \ref gem5MemorySystem "gem5 Memory System" 66 * 67 * The BaseSetAssoc tags provide a base, as well as the functionality 68 * common to any set associative tags. Any derived class must implement 69 * the methods related to the specifics of the actual replacment policy. 70 * These are: 71 * 72 * BlkType* accessBlock(); 73 * BlkType* findVictim(); 74 * void insertBlock(); 75 * void invalidate(); 76 */ 77class BaseSetAssoc : public BaseTags 78{ 79 public: 80 /** Typedef the block type used in this tag store. */ 81 typedef CacheBlk BlkType; 82 /** Typedef the set type used in this tag store. */ 83 typedef CacheSet<CacheBlk> SetType; 84 85 86 protected: 87 /** The associativity of the cache. */ 88 const unsigned assoc; 89 /** The allocatable associativity of the cache (alloc mask). */ 90 unsigned allocAssoc; 91 92 /** The cache blocks. */ 93 std::vector<BlkType> blks; 94 /** The data blocks, 1 per cache block. */ 95 std::unique_ptr<uint8_t[]> dataBlks; 96 97 /** The number of sets in the cache. */ 98 const unsigned numSets; 99 100 /** Whether tags and data are accessed sequentially. */ 101 const bool sequentialAccess; 102 103 /** The cache sets. */ 104 std::vector<SetType> sets; 105 106 /** The amount to shift the address to get the set. */ 107 int setShift; 108 /** The amount to shift the address to get the tag. */ 109 int tagShift; 110 /** Mask out all bits that aren't part of the set index. */ 111 unsigned setMask; 112 113public: 114 115 /** Convenience typedef. */ 116 typedef BaseSetAssocParams Params; 117 118 /** 119 * Construct and initialize this tag store. 120 */ 121 BaseSetAssoc(const Params *p); 122 123 /** 124 * Destructor 125 */ 126 virtual ~BaseSetAssoc() {}; 127 128 /** 129 * Find the cache block given set and way 130 * @param set The set of the block. 131 * @param way The way of the block. 132 * @return The cache block. 133 */ 134 CacheBlk *findBlockBySetAndWay(int set, int way) const override; 135 136 /** 137 * Invalidate the given block. 138 * @param blk The block to invalidate. 139 */ 140 void invalidate(CacheBlk *blk) override 141 { 142 assert(blk); 143 assert(blk->isValid()); 144 tagsInUse--; 145 assert(blk->srcMasterId < cache->system->maxMasters()); 146 occupancies[blk->srcMasterId]--; 147 blk->srcMasterId = Request::invldMasterId; 148 blk->task_id = ContextSwitchTaskId::Unknown; 149 blk->tickInserted = curTick(); 150 } 151 152 /** 153 * Access block and update replacement data. May not succeed, in which case 154 * nullptr is returned. This has all the implications of a cache 155 * access and should only be used as such. Returns the access latency as a 156 * side effect. 157 * @param addr The address to find. 158 * @param is_secure True if the target memory space is secure. 159 * @param lat The access latency. 160 * @return Pointer to the cache block if found. 161 */ 162 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 163 { 164 BlkType *blk = findBlock(addr, is_secure); 165 166 // Access all tags in parallel, hence one in each way. The data side 167 // either accesses all blocks in parallel, or one block sequentially on 168 // a hit. Sequential access with a miss doesn't access data. 169 tagAccesses += allocAssoc; 170 if (sequentialAccess) { 171 if (blk != nullptr) { 172 dataAccesses += 1; 173 } 174 } else { 175 dataAccesses += allocAssoc; 176 } 177 178 if (blk != nullptr) { 179 // If a cache hit 180 lat = accessLatency; 181 // Check if the block to be accessed is available. If not, 182 // apply the accessLatency on top of block->whenReady. 183 if (blk->whenReady > curTick() && 184 cache->ticksToCycles(blk->whenReady - curTick()) > 185 accessLatency) { 186 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 187 accessLatency; 188 } 189 blk->refCount += 1; 190 } else { 191 // If a cache miss 192 lat = lookupLatency; 193 } 194 195 return blk; 196 } 197 198 /** 199 * Finds the given address in the cache, do not update replacement data. 200 * i.e. This is a no-side-effect find of a block. 201 * @param addr The address to find. 202 * @param is_secure True if the target memory space is secure. 203 * @param asid The address space ID. 204 * @return Pointer to the cache block if found. 205 */ 206 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 207 208 /** 209 * Find an invalid block to evict for the address provided. 210 * If there are no invalid blocks, this will return the block 211 * in the least-recently-used position. 212 * @param addr The addr to a find a replacement candidate for. 213 * @return The candidate block. 214 */ 215 CacheBlk* findVictim(Addr addr) override 216 { 217 BlkType *blk = nullptr; 218 int set = extractSet(addr); 219 220 // prefer to evict an invalid block 221 for (int i = 0; i < allocAssoc; ++i) { 222 blk = sets[set].blks[i]; 223 if (!blk->isValid()) 224 break; 225 } 226 227 return blk; 228 } 229 230 /** 231 * Insert the new block into the cache. 232 * @param pkt Packet holding the address to update 233 * @param blk The block to update. 234 */ 235 void insertBlock(PacketPtr pkt, CacheBlk *blk) override 236 { 237 Addr addr = pkt->getAddr(); 238 MasterID master_id = pkt->req->masterId(); 239 uint32_t task_id = pkt->req->taskId(); 240 241 if (!blk->isTouched) {
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