1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <cassert>
52#include <cstring>
| 1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <cassert>
52#include <cstring>
|
53#include <list>
| 53#include <memory>
54#include <vector>
|
54
55#include "mem/cache/base.hh"
56#include "mem/cache/blk.hh"
57#include "mem/cache/tags/base.hh"
58#include "mem/cache/tags/cacheset.hh"
59#include "mem/packet.hh"
60#include "params/BaseSetAssoc.hh"
61
62/**
63 * A BaseSetAssoc cache tag store.
64 * @sa \ref gem5MemorySystem "gem5 Memory System"
65 *
66 * The BaseSetAssoc tags provide a base, as well as the functionality
67 * common to any set associative tags. Any derived class must implement
68 * the methods related to the specifics of the actual replacment policy.
69 * These are:
70 *
71 * BlkType* accessBlock();
72 * BlkType* findVictim();
73 * void insertBlock();
74 * void invalidate();
75 */
76class BaseSetAssoc : public BaseTags
77{
78 public:
79 /** Typedef the block type used in this tag store. */
80 typedef CacheBlk BlkType;
81 /** Typedef the set type used in this tag store. */
82 typedef CacheSet<CacheBlk> SetType;
83
84
85 protected:
86 /** The associativity of the cache. */
87 const unsigned assoc;
88 /** The allocatable associativity of the cache (alloc mask). */
89 unsigned allocAssoc;
| 55
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/tags/base.hh"
59#include "mem/cache/tags/cacheset.hh"
60#include "mem/packet.hh"
61#include "params/BaseSetAssoc.hh"
62
63/**
64 * A BaseSetAssoc cache tag store.
65 * @sa \ref gem5MemorySystem "gem5 Memory System"
66 *
67 * The BaseSetAssoc tags provide a base, as well as the functionality
68 * common to any set associative tags. Any derived class must implement
69 * the methods related to the specifics of the actual replacment policy.
70 * These are:
71 *
72 * BlkType* accessBlock();
73 * BlkType* findVictim();
74 * void insertBlock();
75 * void invalidate();
76 */
77class BaseSetAssoc : public BaseTags
78{
79 public:
80 /** Typedef the block type used in this tag store. */
81 typedef CacheBlk BlkType;
82 /** Typedef the set type used in this tag store. */
83 typedef CacheSet<CacheBlk> SetType;
84
85
86 protected:
87 /** The associativity of the cache. */
88 const unsigned assoc;
89 /** The allocatable associativity of the cache (alloc mask). */
90 unsigned allocAssoc;
|
| 91
92 /** The cache blocks. */
93 std::vector<BlkType> blks;
94 /** The data blocks, 1 per cache block. */
95 std::unique_ptr<uint8_t[]> dataBlks;
96
|
90 /** The number of sets in the cache. */
91 const unsigned numSets;
| 97 /** The number of sets in the cache. */
98 const unsigned numSets;
|
| 99
|
92 /** Whether tags and data are accessed sequentially. */
93 const bool sequentialAccess;
94
95 /** The cache sets. */
| 100 /** Whether tags and data are accessed sequentially. */
101 const bool sequentialAccess;
102
103 /** The cache sets. */
|
96 SetType *sets;
| 104 std::vector<SetType> sets;
|
97
| 105
|
98 /** The cache blocks. */
99 BlkType *blks;
100 /** The data blocks, 1 per cache block. */
101 uint8_t *dataBlks;
102
| |
103 /** The amount to shift the address to get the set. */
104 int setShift;
105 /** The amount to shift the address to get the tag. */
106 int tagShift;
107 /** Mask out all bits that aren't part of the set index. */
108 unsigned setMask;
109
110public:
111
112 /** Convenience typedef. */
113 typedef BaseSetAssocParams Params;
114
115 /**
116 * Construct and initialize this tag store.
117 */
118 BaseSetAssoc(const Params *p);
119
120 /**
121 * Destructor
122 */
| 106 /** The amount to shift the address to get the set. */
107 int setShift;
108 /** The amount to shift the address to get the tag. */
109 int tagShift;
110 /** Mask out all bits that aren't part of the set index. */
111 unsigned setMask;
112
113public:
114
115 /** Convenience typedef. */
116 typedef BaseSetAssocParams Params;
117
118 /**
119 * Construct and initialize this tag store.
120 */
121 BaseSetAssoc(const Params *p);
122
123 /**
124 * Destructor
125 */
|
123 virtual ~BaseSetAssoc();
| 126 virtual ~BaseSetAssoc() {};
|
124
125 /**
126 * Find the cache block given set and way
127 * @param set The set of the block.
128 * @param way The way of the block.
129 * @return The cache block.
130 */
131 CacheBlk *findBlockBySetAndWay(int set, int way) const override;
132
133 /**
134 * Invalidate the given block.
135 * @param blk The block to invalidate.
136 */
137 void invalidate(CacheBlk *blk) override
138 {
139 assert(blk);
140 assert(blk->isValid());
141 tagsInUse--;
142 assert(blk->srcMasterId < cache->system->maxMasters());
143 occupancies[blk->srcMasterId]--;
144 blk->srcMasterId = Request::invldMasterId;
145 blk->task_id = ContextSwitchTaskId::Unknown;
146 blk->tickInserted = curTick();
147 }
148
149 /**
150 * Access block and update replacement data. May not succeed, in which case
151 * nullptr is returned. This has all the implications of a cache
152 * access and should only be used as such. Returns the access latency as a
153 * side effect.
154 * @param addr The address to find.
155 * @param is_secure True if the target memory space is secure.
156 * @param lat The access latency.
157 * @return Pointer to the cache block if found.
158 */
159 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
160 {
161 Addr tag = extractTag(addr);
162 int set = extractSet(addr);
163 BlkType *blk = sets[set].findBlk(tag, is_secure);
164
165 // Access all tags in parallel, hence one in each way. The data side
166 // either accesses all blocks in parallel, or one block sequentially on
167 // a hit. Sequential access with a miss doesn't access data.
168 tagAccesses += allocAssoc;
169 if (sequentialAccess) {
170 if (blk != nullptr) {
171 dataAccesses += 1;
172 }
173 } else {
174 dataAccesses += allocAssoc;
175 }
176
177 if (blk != nullptr) {
178 // If a cache hit
179 lat = accessLatency;
180 // Check if the block to be accessed is available. If not,
181 // apply the accessLatency on top of block->whenReady.
182 if (blk->whenReady > curTick() &&
183 cache->ticksToCycles(blk->whenReady - curTick()) >
184 accessLatency) {
185 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
186 accessLatency;
187 }
188 blk->refCount += 1;
189 } else {
190 // If a cache miss
191 lat = lookupLatency;
192 }
193
194 return blk;
195 }
196
197 /**
198 * Finds the given address in the cache, do not update replacement data.
199 * i.e. This is a no-side-effect find of a block.
200 * @param addr The address to find.
201 * @param is_secure True if the target memory space is secure.
202 * @param asid The address space ID.
203 * @return Pointer to the cache block if found.
204 */
205 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
206
207 /**
208 * Find an invalid block to evict for the address provided.
209 * If there are no invalid blocks, this will return the block
210 * in the least-recently-used position.
211 * @param addr The addr to a find a replacement candidate for.
212 * @return The candidate block.
213 */
214 CacheBlk* findVictim(Addr addr) override
215 {
216 BlkType *blk = nullptr;
217 int set = extractSet(addr);
218
219 // prefer to evict an invalid block
220 for (int i = 0; i < allocAssoc; ++i) {
221 blk = sets[set].blks[i];
222 if (!blk->isValid())
223 break;
224 }
225
226 return blk;
227 }
228
229 /**
230 * Insert the new block into the cache.
231 * @param pkt Packet holding the address to update
232 * @param blk The block to update.
233 */
234 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
235 {
236 Addr addr = pkt->getAddr();
237 MasterID master_id = pkt->req->masterId();
238 uint32_t task_id = pkt->req->taskId();
239
240 if (!blk->isTouched) {
241 tagsInUse++;
242 blk->isTouched = true;
243 if (!warmedUp && tagsInUse.value() >= warmupBound) {
244 warmedUp = true;
245 warmupCycle = curTick();
246 }
247 }
248
249 // If we're replacing a block that was previously valid update
250 // stats for it. This can't be done in findBlock() because a
251 // found block might not actually be replaced there if the
252 // coherence protocol says it can't be.
253 if (blk->isValid()) {
254 replacements[0]++;
255 totalRefs += blk->refCount;
256 ++sampledRefs;
257 blk->refCount = 0;
258
259 // deal with evicted block
260 assert(blk->srcMasterId < cache->system->maxMasters());
261 occupancies[blk->srcMasterId]--;
262
263 blk->invalidate();
264 }
265
266 blk->isTouched = true;
267
268 // Set tag for new block. Caller is responsible for setting status.
269 blk->tag = extractTag(addr);
270
271 // deal with what we are bringing in
272 assert(master_id < cache->system->maxMasters());
273 occupancies[master_id]++;
274 blk->srcMasterId = master_id;
275 blk->task_id = task_id;
276 blk->tickInserted = curTick();
277
278 // We only need to write into one tag and one data block.
279 tagAccesses += 1;
280 dataAccesses += 1;
281 }
282
283 /**
284 * Limit the allocation for the cache ways.
285 * @param ways The maximum number of ways available for replacement.
286 */
287 virtual void setWayAllocationMax(int ways) override
288 {
289 fatal_if(ways < 1, "Allocation limit must be greater than zero");
290 allocAssoc = ways;
291 }
292
293 /**
294 * Get the way allocation mask limit.
295 * @return The maximum number of ways available for replacement.
296 */
297 virtual int getWayAllocationMax() const override
298 {
299 return allocAssoc;
300 }
301
302 /**
303 * Generate the tag from the given address.
304 * @param addr The address to get the tag from.
305 * @return The tag of the address.
306 */
307 Addr extractTag(Addr addr) const override
308 {
309 return (addr >> tagShift);
310 }
311
312 /**
313 * Calculate the set index from the address.
314 * @param addr The address to get the set from.
315 * @return The set index of the address.
316 */
317 int extractSet(Addr addr) const override
318 {
319 return ((addr >> setShift) & setMask);
320 }
321
322 /**
323 * Regenerate the block address from the tag.
324 * @param tag The tag of the block.
325 * @param set The set of the block.
326 * @return The block address.
327 */
328 Addr regenerateBlkAddr(Addr tag, unsigned set) const override
329 {
330 return ((tag << tagShift) | ((Addr)set << setShift));
331 }
332
333 /**
334 * Called at end of simulation to complete average block reference stats.
335 */
336 void cleanupRefs() override;
337
338 /**
339 * Print all tags used
340 */
341 std::string print() const override;
342
343 /**
344 * Called prior to dumping stats to compute task occupancy
345 */
346 void computeStats() override;
347
348 /**
349 * Visit each block in the tag store and apply a visitor to the
350 * block.
351 *
352 * The visitor should be a function (or object that behaves like a
353 * function) that takes a cache block reference as its parameter
354 * and returns a bool. A visitor can request the traversal to be
355 * stopped by returning false, returning true causes it to be
356 * called for the next block in the tag store.
357 *
358 * \param visitor Visitor to call on each block.
359 */
360 void forEachBlk(CacheBlkVisitor &visitor) override {
361 for (unsigned i = 0; i < numSets * assoc; ++i) {
362 if (!visitor(blks[i]))
363 return;
364 }
365 }
366};
367
368#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
| 127
128 /**
129 * Find the cache block given set and way
130 * @param set The set of the block.
131 * @param way The way of the block.
132 * @return The cache block.
133 */
134 CacheBlk *findBlockBySetAndWay(int set, int way) const override;
135
136 /**
137 * Invalidate the given block.
138 * @param blk The block to invalidate.
139 */
140 void invalidate(CacheBlk *blk) override
141 {
142 assert(blk);
143 assert(blk->isValid());
144 tagsInUse--;
145 assert(blk->srcMasterId < cache->system->maxMasters());
146 occupancies[blk->srcMasterId]--;
147 blk->srcMasterId = Request::invldMasterId;
148 blk->task_id = ContextSwitchTaskId::Unknown;
149 blk->tickInserted = curTick();
150 }
151
152 /**
153 * Access block and update replacement data. May not succeed, in which case
154 * nullptr is returned. This has all the implications of a cache
155 * access and should only be used as such. Returns the access latency as a
156 * side effect.
157 * @param addr The address to find.
158 * @param is_secure True if the target memory space is secure.
159 * @param lat The access latency.
160 * @return Pointer to the cache block if found.
161 */
162 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
163 {
164 Addr tag = extractTag(addr);
165 int set = extractSet(addr);
166 BlkType *blk = sets[set].findBlk(tag, is_secure);
167
168 // Access all tags in parallel, hence one in each way. The data side
169 // either accesses all blocks in parallel, or one block sequentially on
170 // a hit. Sequential access with a miss doesn't access data.
171 tagAccesses += allocAssoc;
172 if (sequentialAccess) {
173 if (blk != nullptr) {
174 dataAccesses += 1;
175 }
176 } else {
177 dataAccesses += allocAssoc;
178 }
179
180 if (blk != nullptr) {
181 // If a cache hit
182 lat = accessLatency;
183 // Check if the block to be accessed is available. If not,
184 // apply the accessLatency on top of block->whenReady.
185 if (blk->whenReady > curTick() &&
186 cache->ticksToCycles(blk->whenReady - curTick()) >
187 accessLatency) {
188 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
189 accessLatency;
190 }
191 blk->refCount += 1;
192 } else {
193 // If a cache miss
194 lat = lookupLatency;
195 }
196
197 return blk;
198 }
199
200 /**
201 * Finds the given address in the cache, do not update replacement data.
202 * i.e. This is a no-side-effect find of a block.
203 * @param addr The address to find.
204 * @param is_secure True if the target memory space is secure.
205 * @param asid The address space ID.
206 * @return Pointer to the cache block if found.
207 */
208 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
209
210 /**
211 * Find an invalid block to evict for the address provided.
212 * If there are no invalid blocks, this will return the block
213 * in the least-recently-used position.
214 * @param addr The addr to a find a replacement candidate for.
215 * @return The candidate block.
216 */
217 CacheBlk* findVictim(Addr addr) override
218 {
219 BlkType *blk = nullptr;
220 int set = extractSet(addr);
221
222 // prefer to evict an invalid block
223 for (int i = 0; i < allocAssoc; ++i) {
224 blk = sets[set].blks[i];
225 if (!blk->isValid())
226 break;
227 }
228
229 return blk;
230 }
231
232 /**
233 * Insert the new block into the cache.
234 * @param pkt Packet holding the address to update
235 * @param blk The block to update.
236 */
237 void insertBlock(PacketPtr pkt, CacheBlk *blk) override
238 {
239 Addr addr = pkt->getAddr();
240 MasterID master_id = pkt->req->masterId();
241 uint32_t task_id = pkt->req->taskId();
242
243 if (!blk->isTouched) {
244 tagsInUse++;
245 blk->isTouched = true;
246 if (!warmedUp && tagsInUse.value() >= warmupBound) {
247 warmedUp = true;
248 warmupCycle = curTick();
249 }
250 }
251
252 // If we're replacing a block that was previously valid update
253 // stats for it. This can't be done in findBlock() because a
254 // found block might not actually be replaced there if the
255 // coherence protocol says it can't be.
256 if (blk->isValid()) {
257 replacements[0]++;
258 totalRefs += blk->refCount;
259 ++sampledRefs;
260 blk->refCount = 0;
261
262 // deal with evicted block
263 assert(blk->srcMasterId < cache->system->maxMasters());
264 occupancies[blk->srcMasterId]--;
265
266 blk->invalidate();
267 }
268
269 blk->isTouched = true;
270
271 // Set tag for new block. Caller is responsible for setting status.
272 blk->tag = extractTag(addr);
273
274 // deal with what we are bringing in
275 assert(master_id < cache->system->maxMasters());
276 occupancies[master_id]++;
277 blk->srcMasterId = master_id;
278 blk->task_id = task_id;
279 blk->tickInserted = curTick();
280
281 // We only need to write into one tag and one data block.
282 tagAccesses += 1;
283 dataAccesses += 1;
284 }
285
286 /**
287 * Limit the allocation for the cache ways.
288 * @param ways The maximum number of ways available for replacement.
289 */
290 virtual void setWayAllocationMax(int ways) override
291 {
292 fatal_if(ways < 1, "Allocation limit must be greater than zero");
293 allocAssoc = ways;
294 }
295
296 /**
297 * Get the way allocation mask limit.
298 * @return The maximum number of ways available for replacement.
299 */
300 virtual int getWayAllocationMax() const override
301 {
302 return allocAssoc;
303 }
304
305 /**
306 * Generate the tag from the given address.
307 * @param addr The address to get the tag from.
308 * @return The tag of the address.
309 */
310 Addr extractTag(Addr addr) const override
311 {
312 return (addr >> tagShift);
313 }
314
315 /**
316 * Calculate the set index from the address.
317 * @param addr The address to get the set from.
318 * @return The set index of the address.
319 */
320 int extractSet(Addr addr) const override
321 {
322 return ((addr >> setShift) & setMask);
323 }
324
325 /**
326 * Regenerate the block address from the tag.
327 * @param tag The tag of the block.
328 * @param set The set of the block.
329 * @return The block address.
330 */
331 Addr regenerateBlkAddr(Addr tag, unsigned set) const override
332 {
333 return ((tag << tagShift) | ((Addr)set << setShift));
334 }
335
336 /**
337 * Called at end of simulation to complete average block reference stats.
338 */
339 void cleanupRefs() override;
340
341 /**
342 * Print all tags used
343 */
344 std::string print() const override;
345
346 /**
347 * Called prior to dumping stats to compute task occupancy
348 */
349 void computeStats() override;
350
351 /**
352 * Visit each block in the tag store and apply a visitor to the
353 * block.
354 *
355 * The visitor should be a function (or object that behaves like a
356 * function) that takes a cache block reference as its parameter
357 * and returns a bool. A visitor can request the traversal to be
358 * stopped by returning false, returning true causes it to be
359 * called for the next block in the tag store.
360 *
361 * \param visitor Visitor to call on each block.
362 */
363 void forEachBlk(CacheBlkVisitor &visitor) override {
364 for (unsigned i = 0; i < numSets * assoc; ++i) {
365 if (!visitor(blks[i]))
366 return;
367 }
368 }
369};
370
371#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
|