base_set_assoc.hh (13219:454ecc63338d) | base_set_assoc.hh (13220:78a8391a0f95) |
---|---|
1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 57 unchanged lines hidden (view full) --- 66 * A basic cache tag store. 67 * @sa \ref gem5MemorySystem "gem5 Memory System" 68 * 69 * The BaseSetAssoc placement policy divides the cache into s sets of w 70 * cache lines (ways). 71 */ 72class BaseSetAssoc : public BaseTags 73{ | 1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 57 unchanged lines hidden (view full) --- 66 * A basic cache tag store. 67 * @sa \ref gem5MemorySystem "gem5 Memory System" 68 * 69 * The BaseSetAssoc placement policy divides the cache into s sets of w 70 * cache lines (ways). 71 */ 72class BaseSetAssoc : public BaseTags 73{ |
74 public: 75 /** Typedef the block type used in this tag store. */ 76 typedef CacheBlk BlkType; 77 | |
78 protected: 79 /** The allocatable associativity of the cache (alloc mask). */ 80 unsigned allocAssoc; 81 82 /** The cache blocks. */ | 74 protected: 75 /** The allocatable associativity of the cache (alloc mask). */ 76 unsigned allocAssoc; 77 78 /** The cache blocks. */ |
83 std::vector<BlkType> blks; | 79 std::vector<CacheBlk> blks; |
84 85 /** Whether tags and data are accessed sequentially. */ 86 const bool sequentialAccess; 87 88 /** Replacement policy */ 89 BaseReplacementPolicy *replacementPolicy; 90 91 public: --- 32 unchanged lines hidden (view full) --- 124 * side effect. 125 * @param addr The address to find. 126 * @param is_secure True if the target memory space is secure. 127 * @param lat The access latency. 128 * @return Pointer to the cache block if found. 129 */ 130 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 131 { | 80 81 /** Whether tags and data are accessed sequentially. */ 82 const bool sequentialAccess; 83 84 /** Replacement policy */ 85 BaseReplacementPolicy *replacementPolicy; 86 87 public: --- 32 unchanged lines hidden (view full) --- 120 * side effect. 121 * @param addr The address to find. 122 * @param is_secure True if the target memory space is secure. 123 * @param lat The access latency. 124 * @return Pointer to the cache block if found. 125 */ 126 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 127 { |
132 BlkType *blk = findBlock(addr, is_secure); | 128 CacheBlk *blk = findBlock(addr, is_secure); |
133 134 // Access all tags in parallel, hence one in each way. The data side 135 // either accesses all blocks in parallel, or one block sequentially on 136 // a hit. Sequential access with a miss doesn't access data. 137 tagAccesses += allocAssoc; 138 if (sequentialAccess) { 139 if (blk != nullptr) { 140 dataAccesses += 1; --- 129 unchanged lines hidden --- | 129 130 // Access all tags in parallel, hence one in each way. The data side 131 // either accesses all blocks in parallel, or one block sequentially on 132 // a hit. Sequential access with a miss doesn't access data. 133 tagAccesses += allocAssoc; 134 if (sequentialAccess) { 135 if (blk != nullptr) { 136 dataAccesses += 1; --- 129 unchanged lines hidden --- |