base_set_assoc.hh (10274:68da5ef4bb6f) | base_set_assoc.hh (10693:c0979b2ebda5) |
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1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 164 unchanged lines hidden (view full) --- 173 * @return Pointer to the cache block if found. 174 */ 175 BlkType* accessBlock(Addr addr, bool is_secure, Cycles &lat, 176 int context_src) 177 { 178 Addr tag = extractTag(addr); 179 int set = extractSet(addr); 180 BlkType *blk = sets[set].findBlk(tag, is_secure); | 1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 164 unchanged lines hidden (view full) --- 173 * @return Pointer to the cache block if found. 174 */ 175 BlkType* accessBlock(Addr addr, bool is_secure, Cycles &lat, 176 int context_src) 177 { 178 Addr tag = extractTag(addr); 179 int set = extractSet(addr); 180 BlkType *blk = sets[set].findBlk(tag, is_secure); |
181 lat = hitLatency; | 181 lat = accessLatency;; |
182 183 // Access all tags in parallel, hence one in each way. The data side 184 // either accesses all blocks in parallel, or one block sequentially on 185 // a hit. Sequential access with a miss doesn't access data. 186 tagAccesses += assoc; 187 if (sequentialAccess) { 188 if (blk != NULL) { 189 dataAccesses += 1; 190 } 191 } else { 192 dataAccesses += assoc; 193 } 194 195 if (blk != NULL) { 196 if (blk->whenReady > curTick() 197 && cache->ticksToCycles(blk->whenReady - curTick()) | 182 183 // Access all tags in parallel, hence one in each way. The data side 184 // either accesses all blocks in parallel, or one block sequentially on 185 // a hit. Sequential access with a miss doesn't access data. 186 tagAccesses += assoc; 187 if (sequentialAccess) { 188 if (blk != NULL) { 189 dataAccesses += 1; 190 } 191 } else { 192 dataAccesses += assoc; 193 } 194 195 if (blk != NULL) { 196 if (blk->whenReady > curTick() 197 && cache->ticksToCycles(blk->whenReady - curTick()) |
198 > hitLatency) { | 198 > accessLatency) { |
199 lat = cache->ticksToCycles(blk->whenReady - curTick()); 200 } 201 blk->refCount += 1; 202 } 203 204 return blk; 205 } 206 --- 131 unchanged lines hidden (view full) --- 338 * @return The block address. 339 */ 340 Addr regenerateBlkAddr(Addr tag, unsigned set) const 341 { 342 return ((tag << tagShift) | ((Addr)set << setShift)); 343 } 344 345 /** | 199 lat = cache->ticksToCycles(blk->whenReady - curTick()); 200 } 201 blk->refCount += 1; 202 } 203 204 return blk; 205 } 206 --- 131 unchanged lines hidden (view full) --- 338 * @return The block address. 339 */ 340 Addr regenerateBlkAddr(Addr tag, unsigned set) const 341 { 342 return ((tag << tagShift) | ((Addr)set << setShift)); 343 } 344 345 /** |
346 * Return the hit latency. 347 * @return the hit latency. 348 */ 349 Cycles getHitLatency() const 350 { 351 return hitLatency; 352 } 353 /** | |
354 *iterated through all blocks and clear all locks 355 *Needed to clear all lock tracking at once 356 */ 357 virtual void clearLocks(); 358 359 /** 360 * Called at end of simulation to complete average block reference stats. 361 */ --- 34 unchanged lines hidden --- | 346 *iterated through all blocks and clear all locks 347 *Needed to clear all lock tracking at once 348 */ 349 virtual void clearLocks(); 350 351 /** 352 * Called at end of simulation to complete average block reference stats. 353 */ --- 34 unchanged lines hidden --- |