1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 50 unchanged lines hidden (view full) ---

59#include "mem/cache/tags/cacheset.hh"
60#include "mem/packet.hh"
61#include "params/BaseSetAssoc.hh"
62
63/**
64 * A BaseSetAssoc cache tag store.
65 * @sa \ref gem5MemorySystem "gem5 Memory System"
66 *
67 * The BaseSetAssoc tags provide a base, as well as the functionality
68 * common to any set associative tags. Any derived class must implement
69 * the methods related to the specifics of the actual replacment policy.
70 * These are:
71 *
72 * BlkType* accessBlock();
73 * BlkType* findVictim();
74 * void insertBlock();
75 */
76class BaseSetAssoc : public BaseTags
77{
78 public:
79 /** Typedef the block type used in this tag store. */
80 typedef CacheBlk BlkType;
81 /** Typedef the set type used in this tag store. */
82 typedef CacheSet<CacheBlk> SetType;

--- 21 unchanged lines hidden (view full) ---

104
105 /** The amount to shift the address to get the set. */
106 int setShift;
107 /** The amount to shift the address to get the tag. */
108 int tagShift;
109 /** Mask out all bits that aren't part of the set index. */
110 unsigned setMask;
111
112public:
113
114 /** Convenience typedef. */
115 typedef BaseSetAssocParams Params;
116
117 /**
118 * Construct and initialize this tag store.
119 */
120 BaseSetAssoc(const Params *p);
121

--- 42 unchanged lines hidden (view full) ---

164 // Check if the block to be accessed is available. If not,
165 // apply the accessLatency on top of block->whenReady.
166 if (blk->whenReady > curTick() &&
167 cache->ticksToCycles(blk->whenReady - curTick()) >
168 accessLatency) {
169 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
170 accessLatency;
171 }
172 blk->refCount += 1;
173 } else {
174 // If a cache miss
175 lat = lookupLatency;
176 }
177
178 return blk;
179 }
180
181 /**
182 * Finds the given address in the cache, do not update replacement data.
183 * i.e. This is a no-side-effect find of a block.
184 * @param addr The address to find.
185 * @param is_secure True if the target memory space is secure.
186 * @param asid The address space ID.
187 * @return Pointer to the cache block if found.
188 */
189 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
190
191 /**
192 * Find an invalid block to evict for the address provided.
193 * If there are no invalid blocks, this will return the block
194 * in the least-recently-used position.
195 * @param addr The addr to a find a replacement candidate for.
196 * @return The candidate block.
197 */
198 CacheBlk* findVictim(Addr addr) override
199 {
200 BlkType *blk = nullptr;
201 int set = extractSet(addr);
202
203 // prefer to evict an invalid block
204 for (int i = 0; i < allocAssoc; ++i) {
205 blk = sets[set].blks[i];
206 if (!blk->isValid())
207 break;
208 }
209
210 return blk;
211 }
212
213 /**
214 * Insert the new block into the cache.
215 * @param pkt Packet holding the address to update
216 * @param blk The block to update.
217 */
218 void insertBlock(PacketPtr pkt, CacheBlk *blk) override

--- 18 unchanged lines hidden (view full) ---

237 totalRefs += blk->refCount;
238 ++sampledRefs;
239
240 invalidate(blk);
241 blk->invalidate();
242 }
243
244 // Previous block, if existed, has been removed, and now we have
245 // to insert the new one and mark it as touched
246 tagsInUse++;
247 blk->isTouched = true;
248
249 // Set tag for new block. Caller is responsible for setting status.
250 blk->tag = extractTag(addr);
251
252 // deal with what we are bringing in
253 assert(master_id < cache->system->maxMasters());
254 occupancies[master_id]++;
255 blk->srcMasterId = master_id;
256 blk->task_id = task_id;
257 blk->tickInserted = curTick();
258
259 // We only need to write into one tag and one data block.
260 tagAccesses += 1;
261 dataAccesses += 1;
262 }
263
264 /**
265 * Limit the allocation for the cache ways.
266 * @param ways The maximum number of ways available for replacement.
267 */
268 virtual void setWayAllocationMax(int ways) override
269 {

--- 80 unchanged lines hidden ---