1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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82 typedef std::list<BlkType*> BlkList;
83 /** Typedef the set type used in this tag store. */
84 typedef CacheSet<CacheBlk> SetType;
85
86
87 protected:
88 /** The associativity of the cache. */
89 const unsigned assoc;
90 /** The number of sets in the cache. */
91 const unsigned numSets;
92 /** Whether tags and data are accessed sequentially. */
93 const bool sequentialAccess;
94
95 /** The cache sets. */
96 SetType *sets;
97

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141 */
142 unsigned
143 getSubBlockSize() const
144 {
145 return blkSize;
146 }
147
148 /**
149 * Invalidate the given block.
150 * @param blk The block to invalidate.
151 */
152 void invalidate(CacheBlk *blk)
153 {
154 assert(blk);
155 assert(blk->isValid());
156 tagsInUse--;

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178 Addr tag = extractTag(addr);
179 int set = extractSet(addr);
180 BlkType *blk = sets[set].findBlk(tag, is_secure);
181 lat = accessLatency;;
182
183 // Access all tags in parallel, hence one in each way. The data side
184 // either accesses all blocks in parallel, or one block sequentially on
185 // a hit. Sequential access with a miss doesn't access data.
186 tagAccesses += assoc;
187 if (sequentialAccess) {
188 if (blk != NULL) {
189 dataAccesses += 1;
190 }
191 } else {
192 dataAccesses += assoc;
193 }
194
195 if (blk != NULL) {
196 if (blk->whenReady > curTick()
197 && cache->ticksToCycles(blk->whenReady - curTick())
198 > accessLatency) {
199 lat = cache->ticksToCycles(blk->whenReady - curTick());
200 }

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222 * @return The candidate block.
223 */
224 CacheBlk* findVictim(Addr addr)
225 {
226 BlkType *blk = NULL;
227 int set = extractSet(addr);
228
229 // prefer to evict an invalid block
230 for (int i = 0; i < assoc; ++i) {
231 blk = sets[set].blks[i];
232 if (!blk->isValid()) {
233 break;
234 }
235 }
236
237 return blk;
238 }
239
240 /**
241 * Insert the new block into the cache.
242 * @param pkt Packet holding the address to update

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287 blk->tickInserted = curTick();
288
289 // We only need to write into one tag and one data block.
290 tagAccesses += 1;
291 dataAccesses += 1;
292 }
293
294 /**
295 * Generate the tag from the given address.
296 * @param addr The address to get the tag from.
297 * @return The tag of the address.
298 */
299 Addr extractTag(Addr addr) const
300 {
301 return (addr >> tagShift);
302 }

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