base.hh (12636:9859213e2662) base.hh (12702:27cb33a96e0f)
1/*
2 * Copyright (c) 2012-2014,2016-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Declaration of a common base class for cache tagstore objects.
47 */
48
49#ifndef __MEM_CACHE_TAGS_BASE_HH__
50#define __MEM_CACHE_TAGS_BASE_HH__
51
52#include <string>
53
54#include "base/callback.hh"
55#include "base/statistics.hh"
56#include "mem/cache/blk.hh"
57#include "mem/cache/replacement_policies/base.hh"
58#include "params/BaseTags.hh"
59#include "sim/clocked_object.hh"
60
61class BaseCache;
62
63/**
64 * A common base class of Cache tagstore objects.
65 */
66class BaseTags : public ClockedObject
67{
68 protected:
69 /** The block size of the cache. */
70 const unsigned blkSize;
71 /** Mask out all bits that aren't part of the block offset. */
72 const Addr blkMask;
73 /** The size of the cache. */
74 const unsigned size;
75 /** The tag lookup latency of the cache. */
76 const Cycles lookupLatency;
77 /**
78 * The total access latency of the cache. This latency
79 * is different depending on the cache access mode
80 * (parallel or sequential)
81 */
82 const Cycles accessLatency;
83 /** Pointer to the parent cache. */
84 BaseCache *cache;
85
86 /**
87 * The number of tags that need to be touched to meet the warmup
88 * percentage.
89 */
90 const unsigned warmupBound;
91 /** Marked true when the cache is warmed up. */
92 bool warmedUp;
93
94 /** the number of blocks in the cache */
95 const unsigned numBlocks;
96
97 /** The data blocks, 1 per cache block. */
98 std::unique_ptr<uint8_t[]> dataBlks;
99
100 // Statistics
101 /**
102 * TODO: It would be good if these stats were acquired after warmup.
103 * @addtogroup CacheStatistics
104 * @{
105 */
106
1/*
2 * Copyright (c) 2012-2014,2016-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Declaration of a common base class for cache tagstore objects.
47 */
48
49#ifndef __MEM_CACHE_TAGS_BASE_HH__
50#define __MEM_CACHE_TAGS_BASE_HH__
51
52#include <string>
53
54#include "base/callback.hh"
55#include "base/statistics.hh"
56#include "mem/cache/blk.hh"
57#include "mem/cache/replacement_policies/base.hh"
58#include "params/BaseTags.hh"
59#include "sim/clocked_object.hh"
60
61class BaseCache;
62
63/**
64 * A common base class of Cache tagstore objects.
65 */
66class BaseTags : public ClockedObject
67{
68 protected:
69 /** The block size of the cache. */
70 const unsigned blkSize;
71 /** Mask out all bits that aren't part of the block offset. */
72 const Addr blkMask;
73 /** The size of the cache. */
74 const unsigned size;
75 /** The tag lookup latency of the cache. */
76 const Cycles lookupLatency;
77 /**
78 * The total access latency of the cache. This latency
79 * is different depending on the cache access mode
80 * (parallel or sequential)
81 */
82 const Cycles accessLatency;
83 /** Pointer to the parent cache. */
84 BaseCache *cache;
85
86 /**
87 * The number of tags that need to be touched to meet the warmup
88 * percentage.
89 */
90 const unsigned warmupBound;
91 /** Marked true when the cache is warmed up. */
92 bool warmedUp;
93
94 /** the number of blocks in the cache */
95 const unsigned numBlocks;
96
97 /** The data blocks, 1 per cache block. */
98 std::unique_ptr<uint8_t[]> dataBlks;
99
100 // Statistics
101 /**
102 * TODO: It would be good if these stats were acquired after warmup.
103 * @addtogroup CacheStatistics
104 * @{
105 */
106
107 /** Number of replacements of valid blocks per thread. */
108 Stats::Vector replacements;
109 /** Per cycle average of the number of tags that hold valid data. */
110 Stats::Average tagsInUse;
111
112 /** The total number of references to a block before it is replaced. */
113 Stats::Scalar totalRefs;
114
115 /**
116 * The number of reference counts sampled. This is different from
117 * replacements because we sample all the valid blocks when the simulator
118 * exits.
119 */
120 Stats::Scalar sampledRefs;
121
122 /**
123 * Average number of references to a block before is was replaced.
124 * @todo This should change to an average stat once we have them.
125 */
126 Stats::Formula avgRefs;
127
128 /** The cycle that the warmup percentage was hit. 0 on failure. */
129 Stats::Scalar warmupCycle;
130
131 /** Average occupancy of each requestor using the cache */
132 Stats::AverageVector occupancies;
133
134 /** Average occ % of each requestor using the cache */
135 Stats::Formula avgOccs;
136
137 /** Occupancy of each context/cpu using the cache */
138 Stats::Vector occupanciesTaskId;
139
140 /** Occupancy of each context/cpu using the cache */
141 Stats::Vector2d ageTaskId;
142
143 /** Occ % of each context/cpu using the cache */
144 Stats::Formula percentOccsTaskId;
145
146 /** Number of tags consulted over all accesses. */
147 Stats::Scalar tagAccesses;
148 /** Number of data blocks consulted over all accesses. */
149 Stats::Scalar dataAccesses;
150
151 /**
152 * @}
153 */
154
155 public:
156 typedef BaseTagsParams Params;
157 BaseTags(const Params *p);
158
159 /**
160 * Destructor.
161 */
162 virtual ~BaseTags() {}
163
164 /**
165 * Set the parent cache back pointer.
166 * @param _cache Pointer to parent cache.
167 */
168 void setCache(BaseCache *_cache);
169
170 /**
171 * Register local statistics.
172 */
173 void regStats();
174
175 /**
176 * Average in the reference count for valid blocks when the simulation
177 * exits.
178 */
179 virtual void cleanupRefs() {}
180
181 /**
182 * Computes stats just prior to dump event
183 */
184 virtual void computeStats() {}
185
186 /**
187 * Print all tags used
188 */
189 virtual std::string print() const = 0;
190
191 /**
192 * Find a block using the memory address
193 */
194 virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0;
195
196 /**
197 * Align an address to the block size.
198 * @param addr the address to align.
199 * @return The block address.
200 */
201 Addr blkAlign(Addr addr) const
202 {
203 return addr & ~blkMask;
204 }
205
206 /**
207 * Calculate the block offset of an address.
208 * @param addr the address to get the offset of.
209 * @return the block offset.
210 */
211 int extractBlkOffset(Addr addr) const
212 {
213 return (addr & blkMask);
214 }
215
216 /**
217 * Find the cache block given set and way
218 * @param set The set of the block.
219 * @param way The way of the block.
220 * @return The cache block.
221 */
222 virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0;
223
224 /**
225 * Limit the allocation for the cache ways.
226 * @param ways The maximum number of ways available for replacement.
227 */
228 virtual void setWayAllocationMax(int ways)
229 {
230 panic("This tag class does not implement way allocation limit!\n");
231 }
232
233 /**
234 * Get the way allocation mask limit.
235 * @return The maximum number of ways available for replacement.
236 */
237 virtual int getWayAllocationMax() const
238 {
239 panic("This tag class does not implement way allocation limit!\n");
240 return -1;
241 }
242
243 /**
244 * This function updates the tags when a block is invalidated but
245 * does not invalidate the block itself.
246 * @param blk The block to invalidate.
247 */
248 virtual void invalidate(CacheBlk *blk)
249 {
250 assert(blk);
251 assert(blk->isValid());
252 tagsInUse--;
253 occupancies[blk->srcMasterId]--;
254 }
255
256 /**
257 * Find replacement victim based on address.
258 *
259 * @param addr Address to find a victim for.
260 * @return Cache block to be replaced.
261 */
262 virtual CacheBlk* findVictim(Addr addr) = 0;
263
264 virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
265
266 virtual Addr extractTag(Addr addr) const = 0;
267
268 /**
269 * Insert the new block into the cache and update stats.
270 *
271 * @param pkt Packet holding the address to update
272 * @param blk The block to update.
273 */
274 virtual void insertBlock(PacketPtr pkt, CacheBlk *blk);
275
276 /**
277 * Regenerate the block address.
278 *
279 * @param block The block.
280 * @return the block address.
281 */
282 virtual Addr regenerateBlkAddr(const CacheBlk* blk) const = 0;
283
284 virtual int extractSet(Addr addr) const = 0;
285
286 virtual void forEachBlk(CacheBlkVisitor &visitor) = 0;
287};
288
289class BaseTagsCallback : public Callback
290{
291 BaseTags *tags;
292 public:
293 BaseTagsCallback(BaseTags *t) : tags(t) {}
294 virtual void process() { tags->cleanupRefs(); };
295};
296
297class BaseTagsDumpCallback : public Callback
298{
299 BaseTags *tags;
300 public:
301 BaseTagsDumpCallback(BaseTags *t) : tags(t) {}
302 virtual void process() { tags->computeStats(); };
303};
304
305#endif //__MEM_CACHE_TAGS_BASE_HH__
107 /** Per cycle average of the number of tags that hold valid data. */
108 Stats::Average tagsInUse;
109
110 /** The total number of references to a block before it is replaced. */
111 Stats::Scalar totalRefs;
112
113 /**
114 * The number of reference counts sampled. This is different from
115 * replacements because we sample all the valid blocks when the simulator
116 * exits.
117 */
118 Stats::Scalar sampledRefs;
119
120 /**
121 * Average number of references to a block before is was replaced.
122 * @todo This should change to an average stat once we have them.
123 */
124 Stats::Formula avgRefs;
125
126 /** The cycle that the warmup percentage was hit. 0 on failure. */
127 Stats::Scalar warmupCycle;
128
129 /** Average occupancy of each requestor using the cache */
130 Stats::AverageVector occupancies;
131
132 /** Average occ % of each requestor using the cache */
133 Stats::Formula avgOccs;
134
135 /** Occupancy of each context/cpu using the cache */
136 Stats::Vector occupanciesTaskId;
137
138 /** Occupancy of each context/cpu using the cache */
139 Stats::Vector2d ageTaskId;
140
141 /** Occ % of each context/cpu using the cache */
142 Stats::Formula percentOccsTaskId;
143
144 /** Number of tags consulted over all accesses. */
145 Stats::Scalar tagAccesses;
146 /** Number of data blocks consulted over all accesses. */
147 Stats::Scalar dataAccesses;
148
149 /**
150 * @}
151 */
152
153 public:
154 typedef BaseTagsParams Params;
155 BaseTags(const Params *p);
156
157 /**
158 * Destructor.
159 */
160 virtual ~BaseTags() {}
161
162 /**
163 * Set the parent cache back pointer.
164 * @param _cache Pointer to parent cache.
165 */
166 void setCache(BaseCache *_cache);
167
168 /**
169 * Register local statistics.
170 */
171 void regStats();
172
173 /**
174 * Average in the reference count for valid blocks when the simulation
175 * exits.
176 */
177 virtual void cleanupRefs() {}
178
179 /**
180 * Computes stats just prior to dump event
181 */
182 virtual void computeStats() {}
183
184 /**
185 * Print all tags used
186 */
187 virtual std::string print() const = 0;
188
189 /**
190 * Find a block using the memory address
191 */
192 virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0;
193
194 /**
195 * Align an address to the block size.
196 * @param addr the address to align.
197 * @return The block address.
198 */
199 Addr blkAlign(Addr addr) const
200 {
201 return addr & ~blkMask;
202 }
203
204 /**
205 * Calculate the block offset of an address.
206 * @param addr the address to get the offset of.
207 * @return the block offset.
208 */
209 int extractBlkOffset(Addr addr) const
210 {
211 return (addr & blkMask);
212 }
213
214 /**
215 * Find the cache block given set and way
216 * @param set The set of the block.
217 * @param way The way of the block.
218 * @return The cache block.
219 */
220 virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0;
221
222 /**
223 * Limit the allocation for the cache ways.
224 * @param ways The maximum number of ways available for replacement.
225 */
226 virtual void setWayAllocationMax(int ways)
227 {
228 panic("This tag class does not implement way allocation limit!\n");
229 }
230
231 /**
232 * Get the way allocation mask limit.
233 * @return The maximum number of ways available for replacement.
234 */
235 virtual int getWayAllocationMax() const
236 {
237 panic("This tag class does not implement way allocation limit!\n");
238 return -1;
239 }
240
241 /**
242 * This function updates the tags when a block is invalidated but
243 * does not invalidate the block itself.
244 * @param blk The block to invalidate.
245 */
246 virtual void invalidate(CacheBlk *blk)
247 {
248 assert(blk);
249 assert(blk->isValid());
250 tagsInUse--;
251 occupancies[blk->srcMasterId]--;
252 }
253
254 /**
255 * Find replacement victim based on address.
256 *
257 * @param addr Address to find a victim for.
258 * @return Cache block to be replaced.
259 */
260 virtual CacheBlk* findVictim(Addr addr) = 0;
261
262 virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
263
264 virtual Addr extractTag(Addr addr) const = 0;
265
266 /**
267 * Insert the new block into the cache and update stats.
268 *
269 * @param pkt Packet holding the address to update
270 * @param blk The block to update.
271 */
272 virtual void insertBlock(PacketPtr pkt, CacheBlk *blk);
273
274 /**
275 * Regenerate the block address.
276 *
277 * @param block The block.
278 * @return the block address.
279 */
280 virtual Addr regenerateBlkAddr(const CacheBlk* blk) const = 0;
281
282 virtual int extractSet(Addr addr) const = 0;
283
284 virtual void forEachBlk(CacheBlkVisitor &visitor) = 0;
285};
286
287class BaseTagsCallback : public Callback
288{
289 BaseTags *tags;
290 public:
291 BaseTagsCallback(BaseTags *t) : tags(t) {}
292 virtual void process() { tags->cleanupRefs(); };
293};
294
295class BaseTagsDumpCallback : public Callback
296{
297 BaseTags *tags;
298 public:
299 BaseTagsDumpCallback(BaseTags *t) : tags(t) {}
300 virtual void process() { tags->computeStats(); };
301};
302
303#endif //__MEM_CACHE_TAGS_BASE_HH__