1/*
2 * Copyright (c) 2012-2014,2016-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Declaration of a common base class for cache tagstore objects.
47 */
48
49#ifndef __MEM_CACHE_TAGS_BASE_HH__
50#define __MEM_CACHE_TAGS_BASE_HH__
51
52#include <string>
53
54#include "base/callback.hh"
55#include "base/statistics.hh"
56#include "mem/cache/blk.hh"
57#include "params/BaseTags.hh"
58#include "sim/clocked_object.hh"
59
60class BaseCache;
61
62/**
63 * A common base class of Cache tagstore objects.
64 */
65class BaseTags : public ClockedObject
66{
67 protected:
68 /** The block size of the cache. */
69 const unsigned blkSize;
70 /** Mask out all bits that aren't part of the block offset. */
71 const Addr blkMask;
72 /** The size of the cache. */
73 const unsigned size;
74 /** The tag lookup latency of the cache. */
75 const Cycles lookupLatency;
76 /**
77 * The total access latency of the cache. This latency
78 * is different depending on the cache access mode
79 * (parallel or sequential)
80 */
81 const Cycles accessLatency;
82 /** Pointer to the parent cache. */
83 BaseCache *cache;
84
85 /**
86 * The number of tags that need to be touched to meet the warmup
87 * percentage.
88 */
89 const unsigned warmupBound;
90 /** Marked true when the cache is warmed up. */
91 bool warmedUp;
92
93 /** the number of blocks in the cache */
94 const unsigned numBlocks;
95
96 // Statistics
97 /**
98 * TODO: It would be good if these stats were acquired after warmup.
99 * @addtogroup CacheStatistics
100 * @{
101 */
102
103 /** Number of replacements of valid blocks per thread. */
104 Stats::Vector replacements;
105 /** Per cycle average of the number of tags that hold valid data. */
106 Stats::Average tagsInUse;
107
108 /** The total number of references to a block before it is replaced. */
109 Stats::Scalar totalRefs;
110
111 /**
112 * The number of reference counts sampled. This is different from
113 * replacements because we sample all the valid blocks when the simulator
114 * exits.
115 */
116 Stats::Scalar sampledRefs;
117
118 /**
119 * Average number of references to a block before is was replaced.
120 * @todo This should change to an average stat once we have them.
121 */
122 Stats::Formula avgRefs;
123
124 /** The cycle that the warmup percentage was hit. 0 on failure. */
125 Stats::Scalar warmupCycle;
126
127 /** Average occupancy of each requestor using the cache */
128 Stats::AverageVector occupancies;
129
130 /** Average occ % of each requestor using the cache */
131 Stats::Formula avgOccs;
132
133 /** Occupancy of each context/cpu using the cache */
134 Stats::Vector occupanciesTaskId;
135
136 /** Occupancy of each context/cpu using the cache */
137 Stats::Vector2d ageTaskId;
138
139 /** Occ % of each context/cpu using the cache */
140 Stats::Formula percentOccsTaskId;
141
142 /** Number of tags consulted over all accesses. */
143 Stats::Scalar tagAccesses;
144 /** Number of data blocks consulted over all accesses. */
145 Stats::Scalar dataAccesses;
146
147 /**
148 * @}
149 */
150
151 public:
152 typedef BaseTagsParams Params;
153 BaseTags(const Params *p);
154
155 /**
156 * Destructor.
157 */
158 virtual ~BaseTags() {}
159
160 /**
161 * Set the parent cache back pointer.
162 * @param _cache Pointer to parent cache.
163 */
164 void setCache(BaseCache *_cache);
165
166 /**
167 * Register local statistics.
168 */
169 void regStats();
170
171 /**
172 * Average in the reference count for valid blocks when the simulation
173 * exits.
174 */
175 virtual void cleanupRefs() {}
176
177 /**
178 * Computes stats just prior to dump event
179 */
180 virtual void computeStats() {}
181
182 /**
183 * Print all tags used
184 */
185 virtual std::string print() const = 0;
186
187 /**
188 * Find a block using the memory address
189 */
190 virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0;
191
192 /**
193 * Align an address to the block size.
194 * @param addr the address to align.
195 * @return The block address.
196 */
197 Addr blkAlign(Addr addr) const
198 {
199 return addr & ~blkMask;
200 }
201
202 /**
203 * Calculate the block offset of an address.
204 * @param addr the address to get the offset of.
205 * @return the block offset.
206 */
207 int extractBlkOffset(Addr addr) const
208 {
209 return (addr & blkMask);
210 }
211
212 /**
213 * Find the cache block given set and way
214 * @param set The set of the block.
215 * @param way The way of the block.
216 * @return The cache block.
217 */
218 virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0;
219
220 /**
221 * Limit the allocation for the cache ways.
222 * @param ways The maximum number of ways available for replacement.
223 */
224 virtual void setWayAllocationMax(int ways)
225 {
226 panic("This tag class does not implement way allocation limit!\n");
227 }
228
229 /**
230 * Get the way allocation mask limit.
231 * @return The maximum number of ways available for replacement.
232 */
233 virtual int getWayAllocationMax() const
234 {
235 panic("This tag class does not implement way allocation limit!\n");
236 return -1;
237 }
238
239 /**
240 * This function updates the tags when a block is invalidated but
241 * does not invalidate the block itself.
242 * @param blk The block to invalidate.
243 */
244 virtual void invalidate(CacheBlk *blk)
245 {
246 assert(blk);
247 assert(blk->isValid());
248 tagsInUse--;
249 occupancies[blk->srcMasterId]--;
250 }
251
252 virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
253
254 virtual Addr extractTag(Addr addr) const = 0;
255
256 virtual void insertBlock(PacketPtr pkt, CacheBlk *blk) = 0;
257
| 1/*
2 * Copyright (c) 2012-2014,2016-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Declaration of a common base class for cache tagstore objects.
47 */
48
49#ifndef __MEM_CACHE_TAGS_BASE_HH__
50#define __MEM_CACHE_TAGS_BASE_HH__
51
52#include <string>
53
54#include "base/callback.hh"
55#include "base/statistics.hh"
56#include "mem/cache/blk.hh"
57#include "params/BaseTags.hh"
58#include "sim/clocked_object.hh"
59
60class BaseCache;
61
62/**
63 * A common base class of Cache tagstore objects.
64 */
65class BaseTags : public ClockedObject
66{
67 protected:
68 /** The block size of the cache. */
69 const unsigned blkSize;
70 /** Mask out all bits that aren't part of the block offset. */
71 const Addr blkMask;
72 /** The size of the cache. */
73 const unsigned size;
74 /** The tag lookup latency of the cache. */
75 const Cycles lookupLatency;
76 /**
77 * The total access latency of the cache. This latency
78 * is different depending on the cache access mode
79 * (parallel or sequential)
80 */
81 const Cycles accessLatency;
82 /** Pointer to the parent cache. */
83 BaseCache *cache;
84
85 /**
86 * The number of tags that need to be touched to meet the warmup
87 * percentage.
88 */
89 const unsigned warmupBound;
90 /** Marked true when the cache is warmed up. */
91 bool warmedUp;
92
93 /** the number of blocks in the cache */
94 const unsigned numBlocks;
95
96 // Statistics
97 /**
98 * TODO: It would be good if these stats were acquired after warmup.
99 * @addtogroup CacheStatistics
100 * @{
101 */
102
103 /** Number of replacements of valid blocks per thread. */
104 Stats::Vector replacements;
105 /** Per cycle average of the number of tags that hold valid data. */
106 Stats::Average tagsInUse;
107
108 /** The total number of references to a block before it is replaced. */
109 Stats::Scalar totalRefs;
110
111 /**
112 * The number of reference counts sampled. This is different from
113 * replacements because we sample all the valid blocks when the simulator
114 * exits.
115 */
116 Stats::Scalar sampledRefs;
117
118 /**
119 * Average number of references to a block before is was replaced.
120 * @todo This should change to an average stat once we have them.
121 */
122 Stats::Formula avgRefs;
123
124 /** The cycle that the warmup percentage was hit. 0 on failure. */
125 Stats::Scalar warmupCycle;
126
127 /** Average occupancy of each requestor using the cache */
128 Stats::AverageVector occupancies;
129
130 /** Average occ % of each requestor using the cache */
131 Stats::Formula avgOccs;
132
133 /** Occupancy of each context/cpu using the cache */
134 Stats::Vector occupanciesTaskId;
135
136 /** Occupancy of each context/cpu using the cache */
137 Stats::Vector2d ageTaskId;
138
139 /** Occ % of each context/cpu using the cache */
140 Stats::Formula percentOccsTaskId;
141
142 /** Number of tags consulted over all accesses. */
143 Stats::Scalar tagAccesses;
144 /** Number of data blocks consulted over all accesses. */
145 Stats::Scalar dataAccesses;
146
147 /**
148 * @}
149 */
150
151 public:
152 typedef BaseTagsParams Params;
153 BaseTags(const Params *p);
154
155 /**
156 * Destructor.
157 */
158 virtual ~BaseTags() {}
159
160 /**
161 * Set the parent cache back pointer.
162 * @param _cache Pointer to parent cache.
163 */
164 void setCache(BaseCache *_cache);
165
166 /**
167 * Register local statistics.
168 */
169 void regStats();
170
171 /**
172 * Average in the reference count for valid blocks when the simulation
173 * exits.
174 */
175 virtual void cleanupRefs() {}
176
177 /**
178 * Computes stats just prior to dump event
179 */
180 virtual void computeStats() {}
181
182 /**
183 * Print all tags used
184 */
185 virtual std::string print() const = 0;
186
187 /**
188 * Find a block using the memory address
189 */
190 virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0;
191
192 /**
193 * Align an address to the block size.
194 * @param addr the address to align.
195 * @return The block address.
196 */
197 Addr blkAlign(Addr addr) const
198 {
199 return addr & ~blkMask;
200 }
201
202 /**
203 * Calculate the block offset of an address.
204 * @param addr the address to get the offset of.
205 * @return the block offset.
206 */
207 int extractBlkOffset(Addr addr) const
208 {
209 return (addr & blkMask);
210 }
211
212 /**
213 * Find the cache block given set and way
214 * @param set The set of the block.
215 * @param way The way of the block.
216 * @return The cache block.
217 */
218 virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0;
219
220 /**
221 * Limit the allocation for the cache ways.
222 * @param ways The maximum number of ways available for replacement.
223 */
224 virtual void setWayAllocationMax(int ways)
225 {
226 panic("This tag class does not implement way allocation limit!\n");
227 }
228
229 /**
230 * Get the way allocation mask limit.
231 * @return The maximum number of ways available for replacement.
232 */
233 virtual int getWayAllocationMax() const
234 {
235 panic("This tag class does not implement way allocation limit!\n");
236 return -1;
237 }
238
239 /**
240 * This function updates the tags when a block is invalidated but
241 * does not invalidate the block itself.
242 * @param blk The block to invalidate.
243 */
244 virtual void invalidate(CacheBlk *blk)
245 {
246 assert(blk);
247 assert(blk->isValid());
248 tagsInUse--;
249 occupancies[blk->srcMasterId]--;
250 }
251
252 virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
253
254 virtual Addr extractTag(Addr addr) const = 0;
255
256 virtual void insertBlock(PacketPtr pkt, CacheBlk *blk) = 0;
257
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