1/*
2 * Copyright (c) 2012-2014,2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include <functional>
54#include <string>
55
56#include "base/callback.hh"
57#include "base/logging.hh"
58#include "base/statistics.hh"
59#include "base/types.hh"
60#include "mem/cache/blk.hh"
61#include "mem/packet.hh"
62#include "params/BaseTags.hh"
63#include "sim/clocked_object.hh"
64
65class BaseCache;
66class ReplaceableEntry;
67
68/**
69 * A common base class of Cache tagstore objects.

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280
281 virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
282
283 virtual Addr extractTag(Addr addr) const = 0;
284
285 /**
286 * Insert the new block into the cache and update stats.
287 *
288 * @param pkt Packet holding the address to update
289 * @param blk The block to update.
290 */
291 virtual void insertBlock(const PacketPtr pkt, CacheBlk *blk);
292
293 /**
294 * Regenerate the block address.
295 *
296 * @param block The block.
297 * @return the block address.
298 */
299 virtual Addr regenerateBlkAddr(const CacheBlk* blk) const = 0;

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