1/* 2 * Copyright (c) 2013,2016,2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Ron Dreslinski 42 */ 43 44/** 45 * @file 46 * Definitions of BaseTags. 47 */ 48 49#include "mem/cache/tags/base.hh" 50 51#include <cassert> 52 53#include "base/types.hh" 54#include "mem/cache/replacement_policies/replaceable_entry.hh" 55#include "mem/cache/tags/indexing_policies/base.hh" 56#include "mem/request.hh" 57#include "sim/core.hh" 58#include "sim/sim_exit.hh" 59#include "sim/system.hh" 60 61BaseTags::BaseTags(const Params *p) 62 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1), 63 size(p->size), lookupLatency(p->tag_latency), 64 system(p->system), indexingPolicy(p->indexing_policy), 65 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)), 66 warmedUp(false), numBlocks(p->size / p->block_size), 67 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk 68{ 69} 70 71ReplaceableEntry* 72BaseTags::findBlockBySetAndWay(int set, int way) const 73{ 74 return indexingPolicy->getEntry(set, way); 75} 76 77CacheBlk* 78BaseTags::findBlock(Addr addr, bool is_secure) const 79{ 80 // Extract block tag 81 Addr tag = extractTag(addr); 82 83 // Find possible entries that may contain the given address 84 const std::vector<ReplaceableEntry*> entries = 85 indexingPolicy->getPossibleEntries(addr); 86 87 // Search for block 88 for (const auto& location : entries) { 89 CacheBlk* blk = static_cast<CacheBlk*>(location); 90 if ((blk->tag == tag) && blk->isValid() && 91 (blk->isSecure() == is_secure)) { 92 return blk; 93 } 94 } 95 96 // Did not find block 97 return nullptr; 98} 99 100void
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101BaseTags::insertBlock(const Addr addr, const bool is_secure,
102 const int src_master_ID, const uint32_t task_ID,
103 CacheBlk *blk)
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101BaseTags::insertBlock(const PacketPtr pkt, CacheBlk *blk) |
102{ 103 assert(!blk->isValid()); 104 105 // Previous block, if existed, has been removed, and now we have 106 // to insert the new one
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107 |
108 // Deal with what we are bringing in
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110 assert(src_master_ID < system->maxMasters());
111 occupancies[src_master_ID]++;
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109 MasterID master_id = pkt->req->masterId(); 110 assert(master_id < system->maxMasters()); 111 occupancies[master_id]++; |
112 113 // Insert block with tag, src master id and task id
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114 blk->insert(extractTag(addr), is_secure, src_master_ID, task_ID);
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114 blk->insert(extractTag(pkt->getAddr()), pkt->isSecure(), master_id, 115 pkt->req->taskId()); |
116 117 // Check if cache warm up is done 118 if (!warmedUp && tagsInUse.value() >= warmupBound) { 119 warmedUp = true; 120 warmupCycle = curTick(); 121 } 122 123 // We only need to write into one tag and one data block. 124 tagAccesses += 1; 125 dataAccesses += 1; 126} 127 128Addr 129BaseTags::extractTag(const Addr addr) const 130{ 131 return indexingPolicy->extractTag(addr); 132} 133 134void 135BaseTags::cleanupRefsVisitor(CacheBlk &blk) 136{ 137 if (blk.isValid()) { 138 totalRefs += blk.refCount; 139 ++sampledRefs; 140 } 141} 142 143void 144BaseTags::cleanupRefs() 145{ 146 forEachBlk([this](CacheBlk &blk) { cleanupRefsVisitor(blk); }); 147} 148 149void 150BaseTags::computeStatsVisitor(CacheBlk &blk) 151{ 152 if (blk.isValid()) { 153 assert(blk.task_id < ContextSwitchTaskId::NumTaskId); 154 occupanciesTaskId[blk.task_id]++; 155 assert(blk.tickInserted <= curTick()); 156 Tick age = curTick() - blk.tickInserted; 157 158 int age_index; 159 if (age / SimClock::Int::us < 10) { // <10us 160 age_index = 0; 161 } else if (age / SimClock::Int::us < 100) { // <100us 162 age_index = 1; 163 } else if (age / SimClock::Int::ms < 1) { // <1ms 164 age_index = 2; 165 } else if (age / SimClock::Int::ms < 10) { // <10ms 166 age_index = 3; 167 } else 168 age_index = 4; // >10ms 169 170 ageTaskId[blk.task_id][age_index]++; 171 } 172} 173 174void 175BaseTags::computeStats() 176{ 177 for (unsigned i = 0; i < ContextSwitchTaskId::NumTaskId; ++i) { 178 occupanciesTaskId[i] = 0; 179 for (unsigned j = 0; j < 5; ++j) { 180 ageTaskId[i][j] = 0; 181 } 182 } 183 184 forEachBlk([this](CacheBlk &blk) { computeStatsVisitor(blk); }); 185} 186 187std::string 188BaseTags::print() 189{ 190 std::string str; 191 192 auto print_blk = [&str](CacheBlk &blk) { 193 if (blk.isValid()) 194 str += csprintf("\tBlock: %s\n", blk.print()); 195 }; 196 forEachBlk(print_blk); 197 198 if (str.empty()) 199 str = "no valid tags\n"; 200 201 return str; 202} 203 204void 205BaseTags::regStats() 206{ 207 ClockedObject::regStats(); 208 209 using namespace Stats; 210 211 tagsInUse 212 .name(name() + ".tagsinuse") 213 .desc("Cycle average of tags in use") 214 ; 215 216 totalRefs 217 .name(name() + ".total_refs") 218 .desc("Total number of references to valid blocks.") 219 ; 220 221 sampledRefs 222 .name(name() + ".sampled_refs") 223 .desc("Sample count of references to valid blocks.") 224 ; 225 226 avgRefs 227 .name(name() + ".avg_refs") 228 .desc("Average number of references to valid blocks.") 229 ; 230 231 avgRefs = totalRefs/sampledRefs; 232 233 warmupCycle 234 .name(name() + ".warmup_cycle") 235 .desc("Cycle when the warmup percentage was hit.") 236 ; 237 238 occupancies 239 .init(system->maxMasters()) 240 .name(name() + ".occ_blocks") 241 .desc("Average occupied blocks per requestor") 242 .flags(nozero | nonan) 243 ; 244 for (int i = 0; i < system->maxMasters(); i++) { 245 occupancies.subname(i, system->getMasterName(i)); 246 } 247 248 avgOccs 249 .name(name() + ".occ_percent") 250 .desc("Average percentage of cache occupancy") 251 .flags(nozero | total) 252 ; 253 for (int i = 0; i < system->maxMasters(); i++) { 254 avgOccs.subname(i, system->getMasterName(i)); 255 } 256 257 avgOccs = occupancies / Stats::constant(numBlocks); 258 259 occupanciesTaskId 260 .init(ContextSwitchTaskId::NumTaskId) 261 .name(name() + ".occ_task_id_blocks") 262 .desc("Occupied blocks per task id") 263 .flags(nozero | nonan) 264 ; 265 266 ageTaskId 267 .init(ContextSwitchTaskId::NumTaskId, 5) 268 .name(name() + ".age_task_id_blocks") 269 .desc("Occupied blocks per task id") 270 .flags(nozero | nonan) 271 ; 272 273 percentOccsTaskId 274 .name(name() + ".occ_task_id_percent") 275 .desc("Percentage of cache occupancy per task id") 276 .flags(nozero) 277 ; 278 279 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks); 280 281 tagAccesses 282 .name(name() + ".tag_accesses") 283 .desc("Number of tag accesses") 284 ; 285 286 dataAccesses 287 .name(name() + ".data_accesses") 288 .desc("Number of data accesses") 289 ; 290 291 registerDumpCallback(new BaseTagsDumpCallback(this)); 292 registerExitCallback(new BaseTagsCallback(this)); 293}
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