1/* 2 * Copyright (c) 2013,2016,2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Ron Dreslinski 42 */ 43 44/** 45 * @file 46 * Definitions of BaseTags. 47 */ 48 49#include "mem/cache/tags/base.hh" 50 51#include <cassert> 52 53#include "base/types.hh" 54#include "mem/cache/base.hh" 55#include "mem/request.hh" 56#include "sim/core.hh" 57#include "sim/sim_exit.hh" 58#include "sim/system.hh" 59 60BaseTags::BaseTags(const Params *p) 61 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1), 62 size(p->size), 63 lookupLatency(p->tag_latency), 64 accessLatency(p->sequential_access ? 65 p->tag_latency + p->data_latency : 66 std::max(p->tag_latency, p->data_latency)), 67 cache(nullptr), 68 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)), 69 warmedUp(false), numBlocks(p->size / p->block_size), 70 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk 71{ 72} 73 74void 75BaseTags::setCache(BaseCache *_cache) 76{ 77 assert(!cache); 78 cache = _cache; 79} 80
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110void 111BaseTags::insertBlock(const Addr addr, const bool is_secure, 112 const int src_master_ID, const uint32_t task_ID, 113 CacheBlk *blk) 114{ 115 assert(!blk->isValid()); 116 117 // Previous block, if existed, has been removed, and now we have 118 // to insert the new one 119 // Deal with what we are bringing in 120 assert(src_master_ID < cache->system->maxMasters()); 121 occupancies[src_master_ID]++; 122 123 // Insert block with tag, src master id and task id 124 blk->insert(extractTag(addr), is_secure, src_master_ID, task_ID); 125 126 // Check if cache warm up is done 127 if (!warmedUp && tagsInUse.value() >= warmupBound) { 128 warmedUp = true; 129 warmupCycle = curTick(); 130 } 131 132 // We only need to write into one tag and one data block. 133 tagAccesses += 1; 134 dataAccesses += 1; 135} 136 137void 138BaseTags::cleanupRefsVisitor(CacheBlk &blk) 139{ 140 if (blk.isValid()) { 141 totalRefs += blk.refCount; 142 ++sampledRefs; 143 } 144} 145 146void 147BaseTags::cleanupRefs() 148{ 149 forEachBlk([this](CacheBlk &blk) { cleanupRefsVisitor(blk); }); 150} 151 152void 153BaseTags::computeStatsVisitor(CacheBlk &blk) 154{ 155 if (blk.isValid()) { 156 assert(blk.task_id < ContextSwitchTaskId::NumTaskId); 157 occupanciesTaskId[blk.task_id]++; 158 assert(blk.tickInserted <= curTick()); 159 Tick age = curTick() - blk.tickInserted; 160 161 int age_index; 162 if (age / SimClock::Int::us < 10) { // <10us 163 age_index = 0; 164 } else if (age / SimClock::Int::us < 100) { // <100us 165 age_index = 1; 166 } else if (age / SimClock::Int::ms < 1) { // <1ms 167 age_index = 2; 168 } else if (age / SimClock::Int::ms < 10) { // <10ms 169 age_index = 3; 170 } else 171 age_index = 4; // >10ms 172 173 ageTaskId[blk.task_id][age_index]++; 174 } 175} 176 177void 178BaseTags::computeStats() 179{ 180 for (unsigned i = 0; i < ContextSwitchTaskId::NumTaskId; ++i) { 181 occupanciesTaskId[i] = 0; 182 for (unsigned j = 0; j < 5; ++j) { 183 ageTaskId[i][j] = 0; 184 } 185 } 186 187 forEachBlk([this](CacheBlk &blk) { computeStatsVisitor(blk); }); 188} 189 190std::string 191BaseTags::print() 192{ 193 std::string str; 194 195 auto print_blk = [&str](CacheBlk &blk) { 196 if (blk.isValid()) 197 str += csprintf("\tset: %d way: %d %s\n", blk.set, blk.way, 198 blk.print()); 199 }; 200 forEachBlk(print_blk); 201 202 if (str.empty()) 203 str = "no valid tags\n"; 204 205 return str; 206} 207 208void 209BaseTags::regStats() 210{ 211 ClockedObject::regStats(); 212 213 using namespace Stats; 214 215 tagsInUse 216 .name(name() + ".tagsinuse") 217 .desc("Cycle average of tags in use") 218 ; 219 220 totalRefs 221 .name(name() + ".total_refs") 222 .desc("Total number of references to valid blocks.") 223 ; 224 225 sampledRefs 226 .name(name() + ".sampled_refs") 227 .desc("Sample count of references to valid blocks.") 228 ; 229 230 avgRefs 231 .name(name() + ".avg_refs") 232 .desc("Average number of references to valid blocks.") 233 ; 234 235 avgRefs = totalRefs/sampledRefs; 236 237 warmupCycle 238 .name(name() + ".warmup_cycle") 239 .desc("Cycle when the warmup percentage was hit.") 240 ; 241 242 occupancies 243 .init(cache->system->maxMasters()) 244 .name(name() + ".occ_blocks") 245 .desc("Average occupied blocks per requestor") 246 .flags(nozero | nonan) 247 ; 248 for (int i = 0; i < cache->system->maxMasters(); i++) { 249 occupancies.subname(i, cache->system->getMasterName(i)); 250 } 251 252 avgOccs 253 .name(name() + ".occ_percent") 254 .desc("Average percentage of cache occupancy") 255 .flags(nozero | total) 256 ; 257 for (int i = 0; i < cache->system->maxMasters(); i++) { 258 avgOccs.subname(i, cache->system->getMasterName(i)); 259 } 260 261 avgOccs = occupancies / Stats::constant(numBlocks); 262 263 occupanciesTaskId 264 .init(ContextSwitchTaskId::NumTaskId) 265 .name(name() + ".occ_task_id_blocks") 266 .desc("Occupied blocks per task id") 267 .flags(nozero | nonan) 268 ; 269 270 ageTaskId 271 .init(ContextSwitchTaskId::NumTaskId, 5) 272 .name(name() + ".age_task_id_blocks") 273 .desc("Occupied blocks per task id") 274 .flags(nozero | nonan) 275 ; 276 277 percentOccsTaskId 278 .name(name() + ".occ_task_id_percent") 279 .desc("Percentage of cache occupancy per task id") 280 .flags(nozero) 281 ; 282 283 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks); 284 285 tagAccesses 286 .name(name() + ".tag_accesses") 287 .desc("Number of tag accesses") 288 ; 289 290 dataAccesses 291 .name(name() + ".data_accesses") 292 .desc("Number of data accesses") 293 ; 294 295 registerDumpCallback(new BaseTagsDumpCallback(this)); 296 registerExitCallback(new BaseTagsCallback(this)); 297}
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