1/* 2 * Copyright (c) 2013,2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Ron Dreslinski 42 */ 43 44/** 45 * @file 46 * Definitions of BaseTags. 47 */ 48 49#include "mem/cache/tags/base.hh" 50
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51#include <cassert> 52 53#include "base/types.hh" |
54#include "mem/cache/base.hh"
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55#include "mem/packet.hh" 56#include "mem/request.hh" 57#include "sim/core.hh" |
58#include "sim/sim_exit.hh"
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59#include "sim/system.hh" |
60 61BaseTags::BaseTags(const Params *p) 62 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1), 63 size(p->size), 64 lookupLatency(p->tag_latency), 65 accessLatency(p->sequential_access ? 66 p->tag_latency + p->data_latency : 67 std::max(p->tag_latency, p->data_latency)), 68 cache(nullptr), 69 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)), 70 warmedUp(false), numBlocks(p->size / p->block_size), 71 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk 72{ 73} 74 75void 76BaseTags::setCache(BaseCache *_cache) 77{ 78 assert(!cache); 79 cache = _cache; 80} 81 82void 83BaseTags::insertBlock(PacketPtr pkt, CacheBlk *blk) 84{ 85 assert(!blk->isValid()); 86 87 // Get address 88 Addr addr = pkt->getAddr(); 89 90 // Previous block, if existed, has been removed, and now we have 91 // to insert the new one 92 93 // Deal with what we are bringing in 94 MasterID master_id = pkt->req->masterId(); 95 assert(master_id < cache->system->maxMasters()); 96 occupancies[master_id]++; 97 98 // Insert block with tag, src master id and task id 99 blk->insert(extractTag(addr), pkt->isSecure(), master_id, 100 pkt->req->taskId()); 101 102 tagsInUse++; 103 if (!warmedUp && tagsInUse.value() >= warmupBound) { 104 warmedUp = true; 105 warmupCycle = curTick(); 106 } 107 108 // We only need to write into one tag and one data block. 109 tagAccesses += 1; 110 dataAccesses += 1; 111} 112 113void 114BaseTags::regStats() 115{ 116 ClockedObject::regStats(); 117 118 using namespace Stats; 119 120 tagsInUse 121 .name(name() + ".tagsinuse") 122 .desc("Cycle average of tags in use") 123 ; 124 125 totalRefs 126 .name(name() + ".total_refs") 127 .desc("Total number of references to valid blocks.") 128 ; 129 130 sampledRefs 131 .name(name() + ".sampled_refs") 132 .desc("Sample count of references to valid blocks.") 133 ; 134 135 avgRefs 136 .name(name() + ".avg_refs") 137 .desc("Average number of references to valid blocks.") 138 ; 139 140 avgRefs = totalRefs/sampledRefs; 141 142 warmupCycle 143 .name(name() + ".warmup_cycle") 144 .desc("Cycle when the warmup percentage was hit.") 145 ; 146 147 occupancies 148 .init(cache->system->maxMasters()) 149 .name(name() + ".occ_blocks") 150 .desc("Average occupied blocks per requestor") 151 .flags(nozero | nonan) 152 ; 153 for (int i = 0; i < cache->system->maxMasters(); i++) { 154 occupancies.subname(i, cache->system->getMasterName(i)); 155 } 156 157 avgOccs 158 .name(name() + ".occ_percent") 159 .desc("Average percentage of cache occupancy") 160 .flags(nozero | total) 161 ; 162 for (int i = 0; i < cache->system->maxMasters(); i++) { 163 avgOccs.subname(i, cache->system->getMasterName(i)); 164 } 165 166 avgOccs = occupancies / Stats::constant(numBlocks); 167 168 occupanciesTaskId 169 .init(ContextSwitchTaskId::NumTaskId) 170 .name(name() + ".occ_task_id_blocks") 171 .desc("Occupied blocks per task id") 172 .flags(nozero | nonan) 173 ; 174 175 ageTaskId 176 .init(ContextSwitchTaskId::NumTaskId, 5) 177 .name(name() + ".age_task_id_blocks") 178 .desc("Occupied blocks per task id") 179 .flags(nozero | nonan) 180 ; 181 182 percentOccsTaskId 183 .name(name() + ".occ_task_id_percent") 184 .desc("Percentage of cache occupancy per task id") 185 .flags(nozero) 186 ; 187 188 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks); 189 190 tagAccesses 191 .name(name() + ".tag_accesses") 192 .desc("Number of tag accesses") 193 ; 194 195 dataAccesses 196 .name(name() + ".data_accesses") 197 .desc("Number of data accesses") 198 ; 199 200 registerDumpCallback(new BaseTagsDumpCallback(this)); 201 registerExitCallback(new BaseTagsCallback(this)); 202}
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