1/*
2 * Copyright (c) 2013,2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Definitions of BaseTags.
47 */
48
49#include "mem/cache/tags/base.hh"
50
51#include "cpu/smt.hh" //maxThreadsPerCPU
52#include "mem/cache/base.hh"
53#include "sim/sim_exit.hh"
54
55BaseTags::BaseTags(const Params *p)
56 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
57 size(p->size),
58 lookupLatency(p->tag_latency),
59 accessLatency(p->sequential_access ?
60 p->tag_latency + p->data_latency :
61 std::max(p->tag_latency, p->data_latency)),
62 cache(nullptr),
63 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)),
64 warmedUp(false), numBlocks(p->size / p->block_size),
65 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk
66{
67}
68
69void
70BaseTags::setCache(BaseCache *_cache)
71{
72 assert(!cache);
73 cache = _cache;
74}
75
76void
77BaseTags::insertBlock(PacketPtr pkt, CacheBlk *blk)
78{
79 // Get address
80 Addr addr = pkt->getAddr();
81
82 // Update warmup data
83 if (!blk->isTouched) {
84 if (!warmedUp && tagsInUse.value() >= warmupBound) {
85 warmedUp = true;
86 warmupCycle = curTick();
87 }
88 }
89
90 // If we're replacing a block that was previously valid update
91 // stats for it. This can't be done in findBlock() because a
92 // found block might not actually be replaced there if the
93 // coherence protocol says it can't be.
94 if (blk->isValid()) {
95 replacements[0]++;
96 totalRefs += blk->refCount;
97 ++sampledRefs;
98
99 invalidate(blk);
100 blk->invalidate();
101 }
102
| 1/*
2 * Copyright (c) 2013,2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Definitions of BaseTags.
47 */
48
49#include "mem/cache/tags/base.hh"
50
51#include "cpu/smt.hh" //maxThreadsPerCPU
52#include "mem/cache/base.hh"
53#include "sim/sim_exit.hh"
54
55BaseTags::BaseTags(const Params *p)
56 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
57 size(p->size),
58 lookupLatency(p->tag_latency),
59 accessLatency(p->sequential_access ?
60 p->tag_latency + p->data_latency :
61 std::max(p->tag_latency, p->data_latency)),
62 cache(nullptr),
63 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)),
64 warmedUp(false), numBlocks(p->size / p->block_size),
65 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk
66{
67}
68
69void
70BaseTags::setCache(BaseCache *_cache)
71{
72 assert(!cache);
73 cache = _cache;
74}
75
76void
77BaseTags::insertBlock(PacketPtr pkt, CacheBlk *blk)
78{
79 // Get address
80 Addr addr = pkt->getAddr();
81
82 // Update warmup data
83 if (!blk->isTouched) {
84 if (!warmedUp && tagsInUse.value() >= warmupBound) {
85 warmedUp = true;
86 warmupCycle = curTick();
87 }
88 }
89
90 // If we're replacing a block that was previously valid update
91 // stats for it. This can't be done in findBlock() because a
92 // found block might not actually be replaced there if the
93 // coherence protocol says it can't be.
94 if (blk->isValid()) {
95 replacements[0]++;
96 totalRefs += blk->refCount;
97 ++sampledRefs;
98
99 invalidate(blk);
100 blk->invalidate();
101 }
102
|
123
124 // We only need to write into one tag and one data block.
125 tagAccesses += 1;
126 dataAccesses += 1;
127}
128
129void
130BaseTags::regStats()
131{
132 ClockedObject::regStats();
133
134 using namespace Stats;
135
136 replacements
137 .init(maxThreadsPerCPU)
138 .name(name() + ".replacements")
139 .desc("number of replacements")
140 .flags(total)
141 ;
142
143 tagsInUse
144 .name(name() + ".tagsinuse")
145 .desc("Cycle average of tags in use")
146 ;
147
148 totalRefs
149 .name(name() + ".total_refs")
150 .desc("Total number of references to valid blocks.")
151 ;
152
153 sampledRefs
154 .name(name() + ".sampled_refs")
155 .desc("Sample count of references to valid blocks.")
156 ;
157
158 avgRefs
159 .name(name() + ".avg_refs")
160 .desc("Average number of references to valid blocks.")
161 ;
162
163 avgRefs = totalRefs/sampledRefs;
164
165 warmupCycle
166 .name(name() + ".warmup_cycle")
167 .desc("Cycle when the warmup percentage was hit.")
168 ;
169
170 occupancies
171 .init(cache->system->maxMasters())
172 .name(name() + ".occ_blocks")
173 .desc("Average occupied blocks per requestor")
174 .flags(nozero | nonan)
175 ;
176 for (int i = 0; i < cache->system->maxMasters(); i++) {
177 occupancies.subname(i, cache->system->getMasterName(i));
178 }
179
180 avgOccs
181 .name(name() + ".occ_percent")
182 .desc("Average percentage of cache occupancy")
183 .flags(nozero | total)
184 ;
185 for (int i = 0; i < cache->system->maxMasters(); i++) {
186 avgOccs.subname(i, cache->system->getMasterName(i));
187 }
188
189 avgOccs = occupancies / Stats::constant(numBlocks);
190
191 occupanciesTaskId
192 .init(ContextSwitchTaskId::NumTaskId)
193 .name(name() + ".occ_task_id_blocks")
194 .desc("Occupied blocks per task id")
195 .flags(nozero | nonan)
196 ;
197
198 ageTaskId
199 .init(ContextSwitchTaskId::NumTaskId, 5)
200 .name(name() + ".age_task_id_blocks")
201 .desc("Occupied blocks per task id")
202 .flags(nozero | nonan)
203 ;
204
205 percentOccsTaskId
206 .name(name() + ".occ_task_id_percent")
207 .desc("Percentage of cache occupancy per task id")
208 .flags(nozero)
209 ;
210
211 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
212
213 tagAccesses
214 .name(name() + ".tag_accesses")
215 .desc("Number of tag accesses")
216 ;
217
218 dataAccesses
219 .name(name() + ".data_accesses")
220 .desc("Number of data accesses")
221 ;
222
223 registerDumpCallback(new BaseTagsDumpCallback(this));
224 registerExitCallback(new BaseTagsCallback(this));
225}
| 115
116 // We only need to write into one tag and one data block.
117 tagAccesses += 1;
118 dataAccesses += 1;
119}
120
121void
122BaseTags::regStats()
123{
124 ClockedObject::regStats();
125
126 using namespace Stats;
127
128 replacements
129 .init(maxThreadsPerCPU)
130 .name(name() + ".replacements")
131 .desc("number of replacements")
132 .flags(total)
133 ;
134
135 tagsInUse
136 .name(name() + ".tagsinuse")
137 .desc("Cycle average of tags in use")
138 ;
139
140 totalRefs
141 .name(name() + ".total_refs")
142 .desc("Total number of references to valid blocks.")
143 ;
144
145 sampledRefs
146 .name(name() + ".sampled_refs")
147 .desc("Sample count of references to valid blocks.")
148 ;
149
150 avgRefs
151 .name(name() + ".avg_refs")
152 .desc("Average number of references to valid blocks.")
153 ;
154
155 avgRefs = totalRefs/sampledRefs;
156
157 warmupCycle
158 .name(name() + ".warmup_cycle")
159 .desc("Cycle when the warmup percentage was hit.")
160 ;
161
162 occupancies
163 .init(cache->system->maxMasters())
164 .name(name() + ".occ_blocks")
165 .desc("Average occupied blocks per requestor")
166 .flags(nozero | nonan)
167 ;
168 for (int i = 0; i < cache->system->maxMasters(); i++) {
169 occupancies.subname(i, cache->system->getMasterName(i));
170 }
171
172 avgOccs
173 .name(name() + ".occ_percent")
174 .desc("Average percentage of cache occupancy")
175 .flags(nozero | total)
176 ;
177 for (int i = 0; i < cache->system->maxMasters(); i++) {
178 avgOccs.subname(i, cache->system->getMasterName(i));
179 }
180
181 avgOccs = occupancies / Stats::constant(numBlocks);
182
183 occupanciesTaskId
184 .init(ContextSwitchTaskId::NumTaskId)
185 .name(name() + ".occ_task_id_blocks")
186 .desc("Occupied blocks per task id")
187 .flags(nozero | nonan)
188 ;
189
190 ageTaskId
191 .init(ContextSwitchTaskId::NumTaskId, 5)
192 .name(name() + ".age_task_id_blocks")
193 .desc("Occupied blocks per task id")
194 .flags(nozero | nonan)
195 ;
196
197 percentOccsTaskId
198 .name(name() + ".occ_task_id_percent")
199 .desc("Percentage of cache occupancy per task id")
200 .flags(nozero)
201 ;
202
203 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
204
205 tagAccesses
206 .name(name() + ".tag_accesses")
207 .desc("Number of tag accesses")
208 ;
209
210 dataAccesses
211 .name(name() + ".data_accesses")
212 .desc("Number of data accesses")
213 ;
214
215 registerDumpCallback(new BaseTagsDumpCallback(this));
216 registerExitCallback(new BaseTagsCallback(this));
217}
|