base.cc (12636:9859213e2662) base.cc (12637:bfc3cb9c7e6c)
1/*
2 * Copyright (c) 2013,2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Definitions of BaseTags.
47 */
48
49#include "mem/cache/tags/base.hh"
50
51#include "cpu/smt.hh" //maxThreadsPerCPU
52#include "mem/cache/base.hh"
53#include "sim/sim_exit.hh"
54
1/*
2 * Copyright (c) 2013,2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Definitions of BaseTags.
47 */
48
49#include "mem/cache/tags/base.hh"
50
51#include "cpu/smt.hh" //maxThreadsPerCPU
52#include "mem/cache/base.hh"
53#include "sim/sim_exit.hh"
54
55using namespace std;
56
57BaseTags::BaseTags(const Params *p)
58 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
59 size(p->size),
60 lookupLatency(p->tag_latency),
61 accessLatency(p->sequential_access ?
62 p->tag_latency + p->data_latency :
63 std::max(p->tag_latency, p->data_latency)),
64 cache(nullptr),
65 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)),
66 warmedUp(false), numBlocks(p->size / p->block_size),
67 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk
68{
69}
70
71void
72BaseTags::setCache(BaseCache *_cache)
73{
74 assert(!cache);
75 cache = _cache;
76}
77
78void
79BaseTags::insertBlock(PacketPtr pkt, CacheBlk *blk)
80{
81 // Get address
82 Addr addr = pkt->getAddr();
83
84 // Update warmup data
85 if (!blk->isTouched) {
86 if (!warmedUp && tagsInUse.value() >= warmupBound) {
87 warmedUp = true;
88 warmupCycle = curTick();
89 }
90 }
91
92 // If we're replacing a block that was previously valid update
93 // stats for it. This can't be done in findBlock() because a
94 // found block might not actually be replaced there if the
95 // coherence protocol says it can't be.
96 if (blk->isValid()) {
97 replacements[0]++;
98 totalRefs += blk->refCount;
99 ++sampledRefs;
100
101 invalidate(blk);
102 blk->invalidate();
103 }
104
105 // Previous block, if existed, has been removed, and now we have
106 // to insert the new one
107 tagsInUse++;
108
109 // Set tag for new block. Caller is responsible for setting status.
110 blk->tag = extractTag(addr);
111
112 // Deal with what we are bringing in
113 MasterID master_id = pkt->req->masterId();
114 assert(master_id < cache->system->maxMasters());
115 occupancies[master_id]++;
116 blk->srcMasterId = master_id;
117
118 // Set task id
119 blk->task_id = pkt->req->taskId();
120
121 // We only need to write into one tag and one data block.
122 tagAccesses += 1;
123 dataAccesses += 1;
124}
125
126void
127BaseTags::regStats()
128{
129 ClockedObject::regStats();
130
131 using namespace Stats;
132
133 replacements
134 .init(maxThreadsPerCPU)
135 .name(name() + ".replacements")
136 .desc("number of replacements")
137 .flags(total)
138 ;
139
140 tagsInUse
141 .name(name() + ".tagsinuse")
142 .desc("Cycle average of tags in use")
143 ;
144
145 totalRefs
146 .name(name() + ".total_refs")
147 .desc("Total number of references to valid blocks.")
148 ;
149
150 sampledRefs
151 .name(name() + ".sampled_refs")
152 .desc("Sample count of references to valid blocks.")
153 ;
154
155 avgRefs
156 .name(name() + ".avg_refs")
157 .desc("Average number of references to valid blocks.")
158 ;
159
160 avgRefs = totalRefs/sampledRefs;
161
162 warmupCycle
163 .name(name() + ".warmup_cycle")
164 .desc("Cycle when the warmup percentage was hit.")
165 ;
166
167 occupancies
168 .init(cache->system->maxMasters())
169 .name(name() + ".occ_blocks")
170 .desc("Average occupied blocks per requestor")
171 .flags(nozero | nonan)
172 ;
173 for (int i = 0; i < cache->system->maxMasters(); i++) {
174 occupancies.subname(i, cache->system->getMasterName(i));
175 }
176
177 avgOccs
178 .name(name() + ".occ_percent")
179 .desc("Average percentage of cache occupancy")
180 .flags(nozero | total)
181 ;
182 for (int i = 0; i < cache->system->maxMasters(); i++) {
183 avgOccs.subname(i, cache->system->getMasterName(i));
184 }
185
186 avgOccs = occupancies / Stats::constant(numBlocks);
187
188 occupanciesTaskId
189 .init(ContextSwitchTaskId::NumTaskId)
190 .name(name() + ".occ_task_id_blocks")
191 .desc("Occupied blocks per task id")
192 .flags(nozero | nonan)
193 ;
194
195 ageTaskId
196 .init(ContextSwitchTaskId::NumTaskId, 5)
197 .name(name() + ".age_task_id_blocks")
198 .desc("Occupied blocks per task id")
199 .flags(nozero | nonan)
200 ;
201
202 percentOccsTaskId
203 .name(name() + ".occ_task_id_percent")
204 .desc("Percentage of cache occupancy per task id")
205 .flags(nozero)
206 ;
207
208 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
209
210 tagAccesses
211 .name(name() + ".tag_accesses")
212 .desc("Number of tag accesses")
213 ;
214
215 dataAccesses
216 .name(name() + ".data_accesses")
217 .desc("Number of data accesses")
218 ;
219
220 registerDumpCallback(new BaseTagsDumpCallback(this));
221 registerExitCallback(new BaseTagsCallback(this));
222}
55BaseTags::BaseTags(const Params *p)
56 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
57 size(p->size),
58 lookupLatency(p->tag_latency),
59 accessLatency(p->sequential_access ?
60 p->tag_latency + p->data_latency :
61 std::max(p->tag_latency, p->data_latency)),
62 cache(nullptr),
63 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)),
64 warmedUp(false), numBlocks(p->size / p->block_size),
65 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk
66{
67}
68
69void
70BaseTags::setCache(BaseCache *_cache)
71{
72 assert(!cache);
73 cache = _cache;
74}
75
76void
77BaseTags::insertBlock(PacketPtr pkt, CacheBlk *blk)
78{
79 // Get address
80 Addr addr = pkt->getAddr();
81
82 // Update warmup data
83 if (!blk->isTouched) {
84 if (!warmedUp && tagsInUse.value() >= warmupBound) {
85 warmedUp = true;
86 warmupCycle = curTick();
87 }
88 }
89
90 // If we're replacing a block that was previously valid update
91 // stats for it. This can't be done in findBlock() because a
92 // found block might not actually be replaced there if the
93 // coherence protocol says it can't be.
94 if (blk->isValid()) {
95 replacements[0]++;
96 totalRefs += blk->refCount;
97 ++sampledRefs;
98
99 invalidate(blk);
100 blk->invalidate();
101 }
102
103 // Previous block, if existed, has been removed, and now we have
104 // to insert the new one
105 tagsInUse++;
106
107 // Set tag for new block. Caller is responsible for setting status.
108 blk->tag = extractTag(addr);
109
110 // Deal with what we are bringing in
111 MasterID master_id = pkt->req->masterId();
112 assert(master_id < cache->system->maxMasters());
113 occupancies[master_id]++;
114 blk->srcMasterId = master_id;
115
116 // Set task id
117 blk->task_id = pkt->req->taskId();
118
119 // We only need to write into one tag and one data block.
120 tagAccesses += 1;
121 dataAccesses += 1;
122}
123
124void
125BaseTags::regStats()
126{
127 ClockedObject::regStats();
128
129 using namespace Stats;
130
131 replacements
132 .init(maxThreadsPerCPU)
133 .name(name() + ".replacements")
134 .desc("number of replacements")
135 .flags(total)
136 ;
137
138 tagsInUse
139 .name(name() + ".tagsinuse")
140 .desc("Cycle average of tags in use")
141 ;
142
143 totalRefs
144 .name(name() + ".total_refs")
145 .desc("Total number of references to valid blocks.")
146 ;
147
148 sampledRefs
149 .name(name() + ".sampled_refs")
150 .desc("Sample count of references to valid blocks.")
151 ;
152
153 avgRefs
154 .name(name() + ".avg_refs")
155 .desc("Average number of references to valid blocks.")
156 ;
157
158 avgRefs = totalRefs/sampledRefs;
159
160 warmupCycle
161 .name(name() + ".warmup_cycle")
162 .desc("Cycle when the warmup percentage was hit.")
163 ;
164
165 occupancies
166 .init(cache->system->maxMasters())
167 .name(name() + ".occ_blocks")
168 .desc("Average occupied blocks per requestor")
169 .flags(nozero | nonan)
170 ;
171 for (int i = 0; i < cache->system->maxMasters(); i++) {
172 occupancies.subname(i, cache->system->getMasterName(i));
173 }
174
175 avgOccs
176 .name(name() + ".occ_percent")
177 .desc("Average percentage of cache occupancy")
178 .flags(nozero | total)
179 ;
180 for (int i = 0; i < cache->system->maxMasters(); i++) {
181 avgOccs.subname(i, cache->system->getMasterName(i));
182 }
183
184 avgOccs = occupancies / Stats::constant(numBlocks);
185
186 occupanciesTaskId
187 .init(ContextSwitchTaskId::NumTaskId)
188 .name(name() + ".occ_task_id_blocks")
189 .desc("Occupied blocks per task id")
190 .flags(nozero | nonan)
191 ;
192
193 ageTaskId
194 .init(ContextSwitchTaskId::NumTaskId, 5)
195 .name(name() + ".age_task_id_blocks")
196 .desc("Occupied blocks per task id")
197 .flags(nozero | nonan)
198 ;
199
200 percentOccsTaskId
201 .name(name() + ".occ_task_id_percent")
202 .desc("Percentage of cache occupancy per task id")
203 .flags(nozero)
204 ;
205
206 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
207
208 tagAccesses
209 .name(name() + ".tag_accesses")
210 .desc("Number of tag accesses")
211 ;
212
213 dataAccesses
214 .name(name() + ".data_accesses")
215 .desc("Number of data accesses")
216 ;
217
218 registerDumpCallback(new BaseTagsDumpCallback(this));
219 registerExitCallback(new BaseTagsCallback(this));
220}