base.cc (12753:fe5b2dbe42bb) | base.cc (13215:82cdb8db4643) |
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1/* 2 * Copyright (c) 2013,2016,2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 38 unchanged lines hidden (view full) --- 47 */ 48 49#include "mem/cache/tags/base.hh" 50 51#include <cassert> 52 53#include "base/types.hh" 54#include "mem/cache/base.hh" | 1/* 2 * Copyright (c) 2013,2016,2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 38 unchanged lines hidden (view full) --- 47 */ 48 49#include "mem/cache/tags/base.hh" 50 51#include <cassert> 52 53#include "base/types.hh" 54#include "mem/cache/base.hh" |
55#include "mem/packet.hh" | |
56#include "mem/request.hh" 57#include "sim/core.hh" 58#include "sim/sim_exit.hh" 59#include "sim/system.hh" 60 61BaseTags::BaseTags(const Params *p) 62 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1), 63 size(p->size), --- 11 unchanged lines hidden (view full) --- 75void 76BaseTags::setCache(BaseCache *_cache) 77{ 78 assert(!cache); 79 cache = _cache; 80} 81 82void | 55#include "mem/request.hh" 56#include "sim/core.hh" 57#include "sim/sim_exit.hh" 58#include "sim/system.hh" 59 60BaseTags::BaseTags(const Params *p) 61 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1), 62 size(p->size), --- 11 unchanged lines hidden (view full) --- 74void 75BaseTags::setCache(BaseCache *_cache) 76{ 77 assert(!cache); 78 cache = _cache; 79} 80 81void |
83BaseTags::insertBlock(const PacketPtr pkt, CacheBlk *blk) | 82BaseTags::insertBlock(const Addr addr, const bool is_secure, 83 const int src_master_ID, const uint32_t task_ID, 84 CacheBlk *blk) |
84{ 85 assert(!blk->isValid()); 86 | 85{ 86 assert(!blk->isValid()); 87 |
87 // Get address 88 Addr addr = pkt->getAddr(); 89 | |
90 // Previous block, if existed, has been removed, and now we have 91 // to insert the new one | 88 // Previous block, if existed, has been removed, and now we have 89 // to insert the new one |
92 | |
93 // Deal with what we are bringing in | 90 // Deal with what we are bringing in |
94 MasterID master_id = pkt->req->masterId(); 95 assert(master_id < cache->system->maxMasters()); 96 occupancies[master_id]++; | 91 assert(src_master_ID < cache->system->maxMasters()); 92 occupancies[src_master_ID]++; |
97 98 // Insert block with tag, src master id and task id | 93 94 // Insert block with tag, src master id and task id |
99 blk->insert(extractTag(addr), pkt->isSecure(), master_id, 100 pkt->req->taskId()); | 95 blk->insert(extractTag(addr), is_secure, src_master_ID, task_ID); |
101 | 96 |
97 // Check if cache warm up is done |
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102 if (!warmedUp && tagsInUse.value() >= warmupBound) { 103 warmedUp = true; 104 warmupCycle = curTick(); 105 } 106 107 // We only need to write into one tag and one data block. 108 tagAccesses += 1; 109 dataAccesses += 1; --- 163 unchanged lines hidden --- | 98 if (!warmedUp && tagsInUse.value() >= warmupBound) { 99 warmedUp = true; 100 warmupCycle = curTick(); 101 } 102 103 // We only need to write into one tag and one data block. 104 tagAccesses += 1; 105 dataAccesses += 1; --- 163 unchanged lines hidden --- |