1/*
2 * Copyright (c) 2013,2016,2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Definitions of BaseTags.
47 */
48
49#include "mem/cache/tags/base.hh"
50
51#include <cassert>
52
53#include "base/types.hh"
54#include "mem/cache/base.hh"
55#include "mem/request.hh"
56#include "sim/core.hh"
57#include "sim/sim_exit.hh"
58#include "sim/system.hh"
59
60BaseTags::BaseTags(const Params *p)
61 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
62 size(p->size),
63 lookupLatency(p->tag_latency),
64 accessLatency(p->sequential_access ?
65 p->tag_latency + p->data_latency :
66 std::max(p->tag_latency, p->data_latency)),
67 cache(nullptr),
68 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)),
69 warmedUp(false), numBlocks(p->size / p->block_size),
70 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk
71{
72}
73
74void
75BaseTags::setCache(BaseCache *_cache)
76{
77 assert(!cache);
78 cache = _cache;
79}
80
81void
82BaseTags::insertBlock(const Addr addr, const bool is_secure,
83 const int src_master_ID, const uint32_t task_ID,
84 CacheBlk *blk)
85{
86 assert(!blk->isValid());
87
88 // Previous block, if existed, has been removed, and now we have
89 // to insert the new one
90 // Deal with what we are bringing in
91 assert(src_master_ID < cache->system->maxMasters());
92 occupancies[src_master_ID]++;
93
94 // Insert block with tag, src master id and task id
95 blk->insert(extractTag(addr), is_secure, src_master_ID, task_ID);
96
97 // Check if cache warm up is done
98 if (!warmedUp && tagsInUse.value() >= warmupBound) {
99 warmedUp = true;
100 warmupCycle = curTick();
101 }
102
103 // We only need to write into one tag and one data block.
104 tagAccesses += 1;
105 dataAccesses += 1;
106}
107
108void
109BaseTags::cleanupRefsVisitor(CacheBlk &blk)
110{
111 if (blk.isValid()) {
112 totalRefs += blk.refCount;
113 ++sampledRefs;
114 }
115}
116
117void
118BaseTags::cleanupRefs()
119{
120 forEachBlk([this](CacheBlk &blk) { cleanupRefsVisitor(blk); });
121}
122
123void
124BaseTags::computeStatsVisitor(CacheBlk &blk)
125{
126 if (blk.isValid()) {
127 assert(blk.task_id < ContextSwitchTaskId::NumTaskId);
128 occupanciesTaskId[blk.task_id]++;
129 assert(blk.tickInserted <= curTick());
130 Tick age = curTick() - blk.tickInserted;
131
132 int age_index;
133 if (age / SimClock::Int::us < 10) { // <10us
134 age_index = 0;
135 } else if (age / SimClock::Int::us < 100) { // <100us
136 age_index = 1;
137 } else if (age / SimClock::Int::ms < 1) { // <1ms
138 age_index = 2;
139 } else if (age / SimClock::Int::ms < 10) { // <10ms
140 age_index = 3;
141 } else
142 age_index = 4; // >10ms
143
144 ageTaskId[blk.task_id][age_index]++;
145 }
146}
147
148void
149BaseTags::computeStats()
150{
151 for (unsigned i = 0; i < ContextSwitchTaskId::NumTaskId; ++i) {
152 occupanciesTaskId[i] = 0;
153 for (unsigned j = 0; j < 5; ++j) {
154 ageTaskId[i][j] = 0;
155 }
156 }
157
158 forEachBlk([this](CacheBlk &blk) { computeStatsVisitor(blk); });
159}
160
161std::string
162BaseTags::print()
163{
164 std::string str;
165
166 auto print_blk = [&str](CacheBlk &blk) {
167 if (blk.isValid())
168 str += csprintf("\tset: %d way: %d %s\n", blk.set, blk.way,
169 blk.print());
170 };
171 forEachBlk(print_blk);
172
173 if (str.empty())
174 str = "no valid tags\n";
175
176 return str;
177}
178
179void
180BaseTags::regStats()
181{
182 ClockedObject::regStats();
183
184 using namespace Stats;
185
186 tagsInUse
187 .name(name() + ".tagsinuse")
188 .desc("Cycle average of tags in use")
189 ;
190
191 totalRefs
192 .name(name() + ".total_refs")
193 .desc("Total number of references to valid blocks.")
194 ;
195
196 sampledRefs
197 .name(name() + ".sampled_refs")
198 .desc("Sample count of references to valid blocks.")
199 ;
200
201 avgRefs
202 .name(name() + ".avg_refs")
203 .desc("Average number of references to valid blocks.")
204 ;
205
206 avgRefs = totalRefs/sampledRefs;
207
208 warmupCycle
209 .name(name() + ".warmup_cycle")
210 .desc("Cycle when the warmup percentage was hit.")
211 ;
212
213 occupancies
214 .init(cache->system->maxMasters())
215 .name(name() + ".occ_blocks")
216 .desc("Average occupied blocks per requestor")
217 .flags(nozero | nonan)
218 ;
219 for (int i = 0; i < cache->system->maxMasters(); i++) {
220 occupancies.subname(i, cache->system->getMasterName(i));
221 }
222
223 avgOccs
224 .name(name() + ".occ_percent")
225 .desc("Average percentage of cache occupancy")
226 .flags(nozero | total)
227 ;
228 for (int i = 0; i < cache->system->maxMasters(); i++) {
229 avgOccs.subname(i, cache->system->getMasterName(i));
230 }
231
232 avgOccs = occupancies / Stats::constant(numBlocks);
233
234 occupanciesTaskId
235 .init(ContextSwitchTaskId::NumTaskId)
236 .name(name() + ".occ_task_id_blocks")
237 .desc("Occupied blocks per task id")
238 .flags(nozero | nonan)
239 ;
240
241 ageTaskId
242 .init(ContextSwitchTaskId::NumTaskId, 5)
243 .name(name() + ".age_task_id_blocks")
244 .desc("Occupied blocks per task id")
245 .flags(nozero | nonan)
246 ;
247
248 percentOccsTaskId
249 .name(name() + ".occ_task_id_percent")
250 .desc("Percentage of cache occupancy per task id")
251 .flags(nozero)
252 ;
253
254 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
255
256 tagAccesses
257 .name(name() + ".tag_accesses")
258 .desc("Number of tag accesses")
259 ;
260
261 dataAccesses
262 .name(name() + ".data_accesses")
263 .desc("Number of data accesses")
264 ;
265
266 registerDumpCallback(new BaseTagsDumpCallback(this));
267 registerExitCallback(new BaseTagsCallback(this));
268}