1/*
2 * Copyright (c) 2013,2016,2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Definitions of BaseTags.
47 */
48
49#include "mem/cache/tags/base.hh"
50
51#include <cassert>
52
53#include "base/types.hh"
54#include "mem/cache/base.hh"
55#include "mem/packet.hh"
56#include "mem/request.hh"
57#include "sim/core.hh"
58#include "sim/sim_exit.hh"
59#include "sim/system.hh"
60
61BaseTags::BaseTags(const Params *p)
62 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
63 size(p->size),
64 lookupLatency(p->tag_latency),
65 accessLatency(p->sequential_access ?
66 p->tag_latency + p->data_latency :
67 std::max(p->tag_latency, p->data_latency)),
68 cache(nullptr),
69 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)),
70 warmedUp(false), numBlocks(p->size / p->block_size),
71 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk
72{
73}
74
75void
76BaseTags::setCache(BaseCache *_cache)
77{
78 assert(!cache);
79 cache = _cache;
80}
81
82void
83BaseTags::insertBlock(PacketPtr pkt, CacheBlk *blk)
84{
85 assert(!blk->isValid());
86
87 // Get address
88 Addr addr = pkt->getAddr();
89
90 // Previous block, if existed, has been removed, and now we have
91 // to insert the new one
92
93 // Deal with what we are bringing in
94 MasterID master_id = pkt->req->masterId();
95 assert(master_id < cache->system->maxMasters());
96 occupancies[master_id]++;
97
98 // Insert block with tag, src master id and task id
99 blk->insert(extractTag(addr), pkt->isSecure(), master_id,
100 pkt->req->taskId());
101
102 tagsInUse++;
103 if (!warmedUp && tagsInUse.value() >= warmupBound) {
104 warmedUp = true;
105 warmupCycle = curTick();
106 }
107
108 // We only need to write into one tag and one data block.
109 tagAccesses += 1;
110 dataAccesses += 1;
111}
112
113void
114BaseTags::cleanupRefsVisitor(CacheBlk &blk)
115{
116 if (blk.isValid()) {
117 totalRefs += blk.refCount;
118 ++sampledRefs;
119 }
120}
121
122void
123BaseTags::cleanupRefs()
124{
125 forEachBlk([this](CacheBlk &blk) { cleanupRefsVisitor(blk); });
126}
127
128void
129BaseTags::computeStatsVisitor(CacheBlk &blk)
130{
131 if (blk.isValid()) {
132 assert(blk.task_id < ContextSwitchTaskId::NumTaskId);
133 occupanciesTaskId[blk.task_id]++;
134 assert(blk.tickInserted <= curTick());
135 Tick age = curTick() - blk.tickInserted;
136
137 int age_index;
138 if (age / SimClock::Int::us < 10) { // <10us
139 age_index = 0;
140 } else if (age / SimClock::Int::us < 100) { // <100us
141 age_index = 1;
142 } else if (age / SimClock::Int::ms < 1) { // <1ms
143 age_index = 2;
144 } else if (age / SimClock::Int::ms < 10) { // <10ms
145 age_index = 3;
146 } else
147 age_index = 4; // >10ms
148
149 ageTaskId[blk.task_id][age_index]++;
150 }
151}
152
153void
154BaseTags::computeStats()
155{
156 for (unsigned i = 0; i < ContextSwitchTaskId::NumTaskId; ++i) {
157 occupanciesTaskId[i] = 0;
158 for (unsigned j = 0; j < 5; ++j) {
159 ageTaskId[i][j] = 0;
160 }
161 }
162
163 forEachBlk([this](CacheBlk &blk) { computeStatsVisitor(blk); });
164}
165
166std::string
167BaseTags::print()
168{
169 std::string str;
170
171 auto print_blk = [&str](CacheBlk &blk) {
172 if (blk.isValid())
173 str += csprintf("\tset: %d way: %d %s\n", blk.set, blk.way,
174 blk.print());
175 };
176 forEachBlk(print_blk);
177
178 if (str.empty())
179 str = "no valid tags\n";
180
181 return str;
182}
183
184void
185BaseTags::regStats()
186{
187 ClockedObject::regStats();
188
189 using namespace Stats;
190
191 tagsInUse
192 .name(name() + ".tagsinuse")
193 .desc("Cycle average of tags in use")
194 ;
195
196 totalRefs
197 .name(name() + ".total_refs")
198 .desc("Total number of references to valid blocks.")
199 ;
200
201 sampledRefs
202 .name(name() + ".sampled_refs")
203 .desc("Sample count of references to valid blocks.")
204 ;
205
206 avgRefs
207 .name(name() + ".avg_refs")
208 .desc("Average number of references to valid blocks.")
209 ;
210
211 avgRefs = totalRefs/sampledRefs;
212
213 warmupCycle
214 .name(name() + ".warmup_cycle")
215 .desc("Cycle when the warmup percentage was hit.")
216 ;
217
218 occupancies
219 .init(cache->system->maxMasters())
220 .name(name() + ".occ_blocks")
221 .desc("Average occupied blocks per requestor")
222 .flags(nozero | nonan)
223 ;
224 for (int i = 0; i < cache->system->maxMasters(); i++) {
225 occupancies.subname(i, cache->system->getMasterName(i));
226 }
227
228 avgOccs
229 .name(name() + ".occ_percent")
230 .desc("Average percentage of cache occupancy")
231 .flags(nozero | total)
232 ;
233 for (int i = 0; i < cache->system->maxMasters(); i++) {
234 avgOccs.subname(i, cache->system->getMasterName(i));
235 }
236
237 avgOccs = occupancies / Stats::constant(numBlocks);
238
239 occupanciesTaskId
240 .init(ContextSwitchTaskId::NumTaskId)
241 .name(name() + ".occ_task_id_blocks")
242 .desc("Occupied blocks per task id")
243 .flags(nozero | nonan)
244 ;
245
246 ageTaskId
247 .init(ContextSwitchTaskId::NumTaskId, 5)
248 .name(name() + ".age_task_id_blocks")
249 .desc("Occupied blocks per task id")
250 .flags(nozero | nonan)
251 ;
252
253 percentOccsTaskId
254 .name(name() + ".occ_task_id_percent")
255 .desc("Percentage of cache occupancy per task id")
256 .flags(nozero)
257 ;
258
259 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
260
261 tagAccesses
262 .name(name() + ".tag_accesses")
263 .desc("Number of tag accesses")
264 ;
265
266 dataAccesses
267 .name(name() + ".data_accesses")
268 .desc("Number of data accesses")
269 ;
270
271 registerDumpCallback(new BaseTagsDumpCallback(this));
272 registerExitCallback(new BaseTagsCallback(this));
273}