queue_entry.hh (12727:56c23b54bcb1) queue_entry.hh (13859:4156ac0c7257)
1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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71
72 /** Tick when ready to issue */
73 Tick readyTime;
74
75 /** True if the entry is uncacheable */
76 bool _isUncacheable;
77
78 public:
1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 62 unchanged lines hidden (view full) ---

71
72 /** Tick when ready to issue */
73 Tick readyTime;
74
75 /** True if the entry is uncacheable */
76 bool _isUncacheable;
77
78 public:
79 /**
80 * A queue entry is holding packets that will be serviced as soon as
81 * resources are available. Since multiple references to the same
82 * address can arrive while a packet is not serviced, each packet is
83 * stored in a target containing its availability, order and other info,
84 * and the queue entry stores these similar targets in a list.
85 */
86 class Target {
87 public:
88 const Tick recvTime; //!< Time when request was received (for stats)
89 const Tick readyTime; //!< Time when request is ready to be serviced
90 const Counter order; //!< Global order (for memory consistency mgmt)
91 const PacketPtr pkt; //!< Pending request packet.
79
92
93 /**
94 * Default constructor. Assigns the current tick as the arrival time
95 * of the packet.
96 *
97 * @param _pkt The pending request packet.
98 * @param ready_time The tick at which the packet will be serviceable.
99 * @param _order Global order.
100 */
101 Target(PacketPtr _pkt, Tick ready_time, Counter _order)
102 : recvTime(curTick()), readyTime(ready_time), order(_order),
103 pkt(_pkt)
104 {}
105 };
106
80 /** True if the entry has been sent downstream. */
81 bool inService;
82
83 /** Order number assigned to disambiguate writes and misses. */
84 Counter order;
85
86 /** Block aligned address. */
87 Addr blkAddr;

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100 bool isUncacheable() const { return _isUncacheable; }
101
102 /**
103 * Send this queue entry as a downstream packet, with the exact
104 * behaviour depending on the specific entry type.
105 */
106 virtual bool sendPacket(BaseCache &cache) = 0;
107
107 /** True if the entry has been sent downstream. */
108 bool inService;
109
110 /** Order number assigned to disambiguate writes and misses. */
111 Counter order;
112
113 /** Block aligned address. */
114 Addr blkAddr;

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127 bool isUncacheable() const { return _isUncacheable; }
128
129 /**
130 * Send this queue entry as a downstream packet, with the exact
131 * behaviour depending on the specific entry type.
132 */
133 virtual bool sendPacket(BaseCache &cache) = 0;
134
135 /**
136 * Returns a pointer to the first target.
137 *
138 * @return A pointer to the first target.
139 */
140 virtual Target* getTarget() = 0;
108};
109
110#endif // __MEM_CACHE_QUEUE_ENTRY_HH__
141};
142
143#endif // __MEM_CACHE_QUEUE_ENTRY_HH__