1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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71
72 /** Tick when ready to issue */
73 Tick readyTime;
74
75 /** True if the entry is uncacheable */
76 bool _isUncacheable;
77
78 public:
79
80 /** True if the entry has been sent downstream. */
81 bool inService;
82
83 /** Order number assigned to disambiguate writes and misses. */
84 Counter order;
85
86 /** Block aligned address. */
87 Addr blkAddr;

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100 bool isUncacheable() const { return _isUncacheable; }
101
102 /**
103 * Send this queue entry as a downstream packet, with the exact
104 * behaviour depending on the specific entry type.
105 */
106 virtual bool sendPacket(BaseCache &cache) = 0;
107
108};
109
110#endif // __MEM_CACHE_QUEUE_ENTRY_HH__