1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * Generic queue entry
47 */
48
49#ifndef __MEM_CACHE_QUEUE_ENTRY_HH__
50#define __MEM_CACHE_QUEUE_ENTRY_HH__
51
52#include "base/types.hh"
53#include "mem/packet.hh"
54
55class BaseCache;
56
57/**
58 * A queue entry base class, to be used by both the MSHRs and
59 * write-queue entries.
60 */
61class QueueEntry : public Packet::SenderState
62{
63
64 /**
65 * Consider the Queue a friend to avoid making everything public
66 */
67 template <class Entry>
68 friend class Queue;
69
70 protected:
71
72 /** Tick when ready to issue */
73 Tick readyTime;
74
75 /** True if the entry is uncacheable */
76 bool _isUncacheable;
77
78 public:
79
80 /** True if the entry has been sent downstream. */
81 bool inService;
82
83 /** Order number assigned to disambiguate writes and misses. */
84 Counter order;
85
86 /** Block aligned address. */
87 Addr blkAddr;
88
89 /** Block size of the cache. */
90 unsigned blkSize;
91
92 /** True if the entry targets the secure memory space. */
93 bool isSecure;
94
95 QueueEntry() : readyTime(0), _isUncacheable(false),
96 inService(false), order(0), blkAddr(0), blkSize(0),
97 isSecure(false)
98 {}
99
100 bool isUncacheable() const { return _isUncacheable; }
101
102 /**
103 * Send this queue entry as a downstream packet, with the exact
104 * behaviour depending on the specific entry type.
105 */
106 virtual bool sendPacket(BaseCache &cache) = 0;
107
108};
109
110#endif // __MEM_CACHE_QUEUE_ENTRY_HH__