stride.hh (10028:fb8c44de891a) stride.hh (10053:b0b69dbafc08)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 62 unchanged lines hidden (view full) ---

71 Addr missAddr;
72 bool isSecure;
73 int stride;
74 int confidence;
75 };
76
77 std::list<StrideEntry*> table[Max_Contexts];
78
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 62 unchanged lines hidden (view full) ---

71 Addr missAddr;
72 bool isSecure;
73 int stride;
74 int confidence;
75 };
76
77 std::list<StrideEntry*> table[Max_Contexts];
78
79 bool instTagged;
80
79 public:
80
81 StridePrefetcher(const Params *p)
81 public:
82
83 StridePrefetcher(const Params *p)
82 : BasePrefetcher(p)
84 : BasePrefetcher(p), instTagged(p->inst_tagged)
83 {
84 }
85
86 ~StridePrefetcher() {}
87
88 void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
89 std::list<Cycles> &delays);
90};
91
92#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
85 {
86 }
87
88 ~StridePrefetcher() {}
89
90 void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
91 std::list<Cycles> &delays);
92};
93
94#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__