1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Describes a strided prefetcher.
34 */
35
36#ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
38
39#include "mem/cache/prefetch/base.hh"
40
41class StridePrefetcher : public BasePrefetcher
42{
43 protected:
44
45 class strideEntry
46 {
47 public:
48 Addr IAddr;
49 Addr MAddr;
50 int stride;
51 int64_t confidence;
52
| 1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Describes a strided prefetcher.
34 */
35
36#ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
38
39#include "mem/cache/prefetch/base.hh"
40
41class StridePrefetcher : public BasePrefetcher
42{
43 protected:
44
45 class strideEntry
46 {
47 public:
48 Addr IAddr;
49 Addr MAddr;
50 int stride;
51 int64_t confidence;
52
|
54 {
55 if (a.confidence == b.confidence) {
56 return true; //??????
57 }
58 else return a.confidence < b.confidence;
59 }*/
60 };
61 Addr* lastMissAddr[64/*MAX_CPUS*/];
62
63 std::list<strideEntry*> table[64/*MAX_CPUS*/];
64 Tick latency;
65 int degree;
66 bool useCPUId;
67
68
69 public:
70
71 StridePrefetcher(const BaseCacheParams *p)
72 : BasePrefetcher(p), latency(p->prefetch_latency),
73 degree(p->prefetch_degree), useCPUId(p->prefetch_use_cpu_id)
74 {
75 }
76
77 ~StridePrefetcher() {}
78
79 void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
80 std::list<Tick> &delays);
81};
82
83#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
| 54 {
55 if (a.confidence == b.confidence) {
56 return true; //??????
57 }
58 else return a.confidence < b.confidence;
59 }*/
60 };
61 Addr* lastMissAddr[64/*MAX_CPUS*/];
62
63 std::list<strideEntry*> table[64/*MAX_CPUS*/];
64 Tick latency;
65 int degree;
66 bool useCPUId;
67
68
69 public:
70
71 StridePrefetcher(const BaseCacheParams *p)
72 : BasePrefetcher(p), latency(p->prefetch_latency),
73 degree(p->prefetch_degree), useCPUId(p->prefetch_use_cpu_id)
74 {
75 }
76
77 ~StridePrefetcher() {}
78
79 void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
80 std::list<Tick> &delays);
81};
82
83#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
|