1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 */
42
43/**
44 * @file
45 * Describes a strided prefetcher.
46 */
47
48#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__
49#define __MEM_CACHE_PREFETCH_STRIDE_HH__
50
51#include <string>
52#include <unordered_map>
| 1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 */
42
43/**
44 * @file
45 * Describes a strided prefetcher.
46 */
47
48#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__
49#define __MEM_CACHE_PREFETCH_STRIDE_HH__
50
51#include <string>
52#include <unordered_map>
|
| 53#include <vector>
|
53
54#include "base/types.hh"
55#include "mem/cache/prefetch/queued.hh"
56#include "mem/packet.hh"
57
58struct StridePrefetcherParams;
59
60class StridePrefetcher : public QueuedPrefetcher
61{
62 protected:
63 const int maxConf;
64 const int threshConf;
65 const int minConf;
66 const int startConf;
67
68 const int pcTableAssoc;
69 const int pcTableSets;
70
71 const bool useMasterId;
72
73 const int degree;
74
75 struct StrideEntry
76 {
77 StrideEntry() : instAddr(0), lastAddr(0), isSecure(false), stride(0),
78 confidence(0)
79 { }
80
81 Addr instAddr;
82 Addr lastAddr;
83 bool isSecure;
84 int stride;
85 int confidence;
86 };
87
88 class PCTable
89 {
90 public:
91 PCTable(int assoc, int sets, const std::string name) :
92 pcTableAssoc(assoc), pcTableSets(sets), _name(name) {}
| 54
55#include "base/types.hh"
56#include "mem/cache/prefetch/queued.hh"
57#include "mem/packet.hh"
58
59struct StridePrefetcherParams;
60
61class StridePrefetcher : public QueuedPrefetcher
62{
63 protected:
64 const int maxConf;
65 const int threshConf;
66 const int minConf;
67 const int startConf;
68
69 const int pcTableAssoc;
70 const int pcTableSets;
71
72 const bool useMasterId;
73
74 const int degree;
75
76 struct StrideEntry
77 {
78 StrideEntry() : instAddr(0), lastAddr(0), isSecure(false), stride(0),
79 confidence(0)
80 { }
81
82 Addr instAddr;
83 Addr lastAddr;
84 bool isSecure;
85 int stride;
86 int confidence;
87 };
88
89 class PCTable
90 {
91 public:
92 PCTable(int assoc, int sets, const std::string name) :
93 pcTableAssoc(assoc), pcTableSets(sets), _name(name) {}
|
93 StrideEntry** operator[] (int context) {
| 94
95 std::vector<std::vector<StrideEntry>>& operator[] (int context) {
|
94 auto it = entries.find(context);
95 if (it != entries.end())
96 return it->second;
97
98 return allocateNewContext(context);
99 }
100
101 ~PCTable();
102 private:
103 const std::string name() {return _name; }
104 const int pcTableAssoc;
105 const int pcTableSets;
106 const std::string _name;
| 96 auto it = entries.find(context);
97 if (it != entries.end())
98 return it->second;
99
100 return allocateNewContext(context);
101 }
102
103 ~PCTable();
104 private:
105 const std::string name() {return _name; }
106 const int pcTableAssoc;
107 const int pcTableSets;
108 const std::string _name;
|
107 std::unordered_map<int, StrideEntry**> entries;
| 109 std::unordered_map<int, std::vector<std::vector<StrideEntry>>> entries;
|
108
| 110
|
109 StrideEntry** allocateNewContext(int context);
| 111 std::vector<std::vector<StrideEntry>>& allocateNewContext(int context);
|
110 };
111 PCTable pcTable;
112
113 /**
114 * Search for an entry in the pc table.
115 *
116 * @param pc The PC to look for.
117 * @param is_secure True if the target memory space is secure.
118 * @param master_id The context.
119 * @return Pointer to the entry.
120 */
121 StrideEntry* findEntry(Addr pc, bool is_secure, int master_id);
122
123 StrideEntry* pcTableVictim(Addr pc, int master_id);
124
125 Addr pcHash(Addr pc) const;
126 public:
127
128 StridePrefetcher(const StridePrefetcherParams *p);
129
130 void calculatePrefetch(const PacketPtr &pkt,
131 std::vector<AddrPriority> &addresses) override;
132};
133
134#endif // __MEM_CACHE_PREFETCH_STRIDE_HH__
| 112 };
113 PCTable pcTable;
114
115 /**
116 * Search for an entry in the pc table.
117 *
118 * @param pc The PC to look for.
119 * @param is_secure True if the target memory space is secure.
120 * @param master_id The context.
121 * @return Pointer to the entry.
122 */
123 StrideEntry* findEntry(Addr pc, bool is_secure, int master_id);
124
125 StrideEntry* pcTableVictim(Addr pc, int master_id);
126
127 Addr pcHash(Addr pc) const;
128 public:
129
130 StridePrefetcher(const StridePrefetcherParams *p);
131
132 void calculatePrefetch(const PacketPtr &pkt,
133 std::vector<AddrPriority> &addresses) override;
134};
135
136#endif // __MEM_CACHE_PREFETCH_STRIDE_HH__
|