1/*
| 1/*
|
2 * Copyright (c) 2012-2013 ARM Limited
| 2 * Copyright (c) 2012-2013, 2015 ARM Limited
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 */
42
43/**
44 * @file
45 * Describes a strided prefetcher.
46 */
47
48#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__
49#define __MEM_CACHE_PREFETCH_STRIDE_HH__
50
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 */
42
43/**
44 * @file
45 * Describes a strided prefetcher.
46 */
47
48#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__
49#define __MEM_CACHE_PREFETCH_STRIDE_HH__
50
|
| 51#include "base/hashmap.hh"
|
51#include "mem/cache/prefetch/queued.hh"
52#include "params/StridePrefetcher.hh"
53
54class StridePrefetcher : public QueuedPrefetcher
55{
56 protected:
| 52#include "mem/cache/prefetch/queued.hh"
53#include "params/StridePrefetcher.hh"
54
55class StridePrefetcher : public QueuedPrefetcher
56{
57 protected:
|
57 static const int maxContexts = 64;
58
| |
59 const int maxConf;
60 const int threshConf;
61 const int minConf;
62 const int startConf;
63
64 const int pcTableAssoc;
65 const int pcTableSets;
66
67 const bool useMasterId;
68
69 const int degree;
70
71 struct StrideEntry
72 {
73 StrideEntry() : instAddr(0), lastAddr(0), isSecure(false), stride(0),
74 confidence(0)
75 { }
76
77 Addr instAddr;
78 Addr lastAddr;
79 bool isSecure;
80 int stride;
81 int confidence;
82 };
83
| 58 const int maxConf;
59 const int threshConf;
60 const int minConf;
61 const int startConf;
62
63 const int pcTableAssoc;
64 const int pcTableSets;
65
66 const bool useMasterId;
67
68 const int degree;
69
70 struct StrideEntry
71 {
72 StrideEntry() : instAddr(0), lastAddr(0), isSecure(false), stride(0),
73 confidence(0)
74 { }
75
76 Addr instAddr;
77 Addr lastAddr;
78 bool isSecure;
79 int stride;
80 int confidence;
81 };
82
|
84 StrideEntry **pcTable[maxContexts];
| 83 class PCTable
84 {
85 public:
86 PCTable(int assoc, int sets, const std::string name) :
87 pcTableAssoc(assoc), pcTableSets(sets), _name(name) {}
88 StrideEntry** operator[] (int context) {
89 auto it = entries.find(context);
90 if (it != entries.end())
91 return it->second;
|
85
| 92
|
| 93 return allocateNewContext(context);
94 }
95
96 ~PCTable();
97 private:
98 const std::string name() {return _name; }
99 const int pcTableAssoc;
100 const int pcTableSets;
101 const std::string _name;
102 m5::hash_map<int, StrideEntry**> entries;
103
104 StrideEntry** allocateNewContext(int context);
105 };
106 PCTable pcTable;
107
|
86 bool pcTableHit(Addr pc, bool is_secure, int master_id, StrideEntry* &entry);
87 StrideEntry* pcTableVictim(Addr pc, int master_id);
88
89 Addr pcHash(Addr pc) const;
90 public:
91
92 StridePrefetcher(const StridePrefetcherParams *p);
| 108 bool pcTableHit(Addr pc, bool is_secure, int master_id, StrideEntry* &entry);
109 StrideEntry* pcTableVictim(Addr pc, int master_id);
110
111 Addr pcHash(Addr pc) const;
112 public:
113
114 StridePrefetcher(const StridePrefetcherParams *p);
|
93 ~StridePrefetcher();
| |
94
95 void calculatePrefetch(const PacketPtr &pkt, std::vector<Addr> &addresses);
96};
97
98#endif // __MEM_CACHE_PREFETCH_STRIDE_HH__
| 115
116 void calculatePrefetch(const PacketPtr &pkt, std::vector<Addr> &addresses);
117};
118
119#endif // __MEM_CACHE_PREFETCH_STRIDE_HH__
|