1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31/**
32 * @file
33 * Describes a strided prefetcher.
34 */
35
36#ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
38
39#include "mem/cache/prefetch/base.hh"
40
41class StridePrefetcher : public BasePrefetcher
42{
43 protected:
44
45 class strideEntry
46 {
47 public:
48 Addr IAddr;
49 Addr MAddr;
50 int stride;
51 int64_t confidence;
52
53/* bool operator < (strideEntry a,strideEntry b)
54 {
55 if (a.confidence == b.confidence) {
56 return true; //??????
57 }
58 else return a.confidence < b.confidence;
59 }*/
60 };
61 Addr* lastMissAddr[64/*MAX_CPUS*/];
62
63 std::list<strideEntry*> table[64/*MAX_CPUS*/];
64 Tick latency;
65 int degree;
66 bool useContextId;
67
68
69 public:
70
71 StridePrefetcher(const BaseCacheParams *p)
72 : BasePrefetcher(p), latency(p->prefetch_latency),
73 degree(p->prefetch_degree), useContextId(p->prefetch_use_cpu_id)
74 {
75 }
76
77 ~StridePrefetcher() {}
78
79 void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
80 std::list<Tick> &delays);
81};
82
83#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__