stride.cc (5714:76abee886def) | stride.cc (5875:d82be3235ab4) |
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1/* 2 * Copyright (c) 2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 * Steve Reinhardt 30 */ 31 32/** 33 * @file 34 * Stride Prefetcher template instantiations. 35 */ 36 | 1/* 2 * Copyright (c) 2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 * Steve Reinhardt 30 */ 31 32/** 33 * @file 34 * Stride Prefetcher template instantiations. 35 */ 36 |
37#include "base/trace.hh" |
|
37#include "mem/cache/prefetch/stride.hh" 38 39void 40StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, 41 std::list<Tick> &delays) 42{ | 38#include "mem/cache/prefetch/stride.hh" 39 40void 41StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, 42 std::list<Tick> &delays) 43{ |
43// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1); 44 int contextId = pkt->req->contextId(); 45 if (!useContextId) contextId = 0; | 44 if (!pkt->req->hasPC()) { 45 DPRINTF(HWPrefetch, "ignoring request with no PC"); 46 return; 47 } |
46 | 48 |
47 /* Scan Table for IAddr Match */ 48/* std::list<strideEntry*>::iterator iter; 49 for (iter=table[contextId].begin(); 50 iter !=table[contextId].end(); 51 iter++) { 52 if ((*iter)->IAddr == pkt->pc) break; 53 } | 49 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); 50 int ctx_id = useContextId ? pkt->req->contextId() : 0; 51 Addr pc = pkt->req->getPC(); 52 assert(ctx_id < Max_Contexts); 53 std::list<StrideEntry*> &tab = table[ctx_id]; |
54 | 54 |
55 if (iter != table[contextId].end()) { 56 //Hit in table | 55 /* Scan Table for instAddr Match */ 56 std::list<StrideEntry*>::iterator iter; 57 for (iter = tab.begin(); iter != tab.end(); iter++) { 58 if ((*iter)->instAddr == pc) 59 break; 60 } |
57 | 61 |
58 int newStride = blkAddr - (*iter)->MAddr; 59 if (newStride == (*iter)->stride) { 60 (*iter)->confidence++; 61 } 62 else { 63 (*iter)->stride = newStride; 64 (*iter)->confidence--; 65 } | 62 if (iter != tab.end()) { 63 // Hit in table |
66 | 64 |
67 (*iter)->MAddr = blkAddr; | 65 int new_stride = blk_addr - (*iter)->missAddr; 66 bool stride_match = (new_stride == (*iter)->stride); |
68 | 67 |
69 for (int d=1; d <= degree; d++) { 70 Addr newAddr = blkAddr + d * newStride; 71 if (this->pageStop && 72 (blkAddr & ~(TheISA::VMPageSize - 1)) != 73 (newAddr & ~(TheISA::VMPageSize - 1))) 74 { 75 //Spanned the page, so now stop 76 this->pfSpanPage += degree - d + 1; 77 return; 78 } 79 else 80 { 81 addresses.push_back(newAddr); 82 delays.push_back(latency); 83 } 84 } 85 } 86 else { 87 //Miss in table 88 //Find lowest confidence and replace | 68 if (stride_match && new_stride != 0) { 69 if ((*iter)->confidence < Max_Conf) 70 (*iter)->confidence++; 71 } else { 72 (*iter)->stride = new_stride; 73 if ((*iter)->confidence > Min_Conf) 74 (*iter)->confidence = 0; 75 } |
89 | 76 |
90 } 91*/ | 77 DPRINTF(HWPrefetch, "hit: PC %x blk_addr %x stride %d (%s), conf %d\n", 78 pc, blk_addr, new_stride, stride_match ? "match" : "change", 79 (*iter)->confidence); 80 81 (*iter)->missAddr = blk_addr; 82 83 if ((*iter)->confidence <= 0) 84 return; 85 86 for (int d = 1; d <= degree; d++) { 87 Addr new_addr = blk_addr + d * new_stride; 88 if (pageStop && !samePage(blk_addr, new_addr)) { 89 // Spanned the page, so now stop 90 pfSpanPage += degree - d + 1; 91 return; 92 } else { 93 DPRINTF(HWPrefetch, " queuing prefetch to %x @ %d\n", 94 new_addr, latency); 95 addresses.push_back(new_addr); 96 delays.push_back(latency); 97 } 98 } 99 } else { 100 // Miss in table 101 // Find lowest confidence and replace 102 103 DPRINTF(HWPrefetch, "miss: PC %x blk_addr %x\n", pc, blk_addr); 104 105 if (tab.size() >= 256) { //set default table size is 256 106 std::list<StrideEntry*>::iterator min_pos = tab.begin(); 107 int min_conf = (*min_pos)->confidence; 108 for (iter = min_pos, ++iter; iter != tab.end(); ++iter) { 109 if ((*iter)->confidence < min_conf){ 110 min_pos = iter; 111 min_conf = (*iter)->confidence; 112 } 113 } 114 DPRINTF(HWPrefetch, " replacing PC %x\n", (*min_pos)->instAddr); 115 tab.erase(min_pos); 116 } 117 118 StrideEntry *new_entry = new StrideEntry; 119 new_entry->instAddr = pc; 120 new_entry->missAddr = blk_addr; 121 new_entry->stride = 0; 122 new_entry->confidence = 0; 123 tab.push_back(new_entry); 124 } |
92} | 125} |