1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Steve Reinhardt
42 */
43
44/**
45 * @file
46 * Stride Prefetcher template instantiations.
47 */
48
49#include "mem/cache/prefetch/stride.hh"
50
51#include <cassert>
52
53#include "base/intmath.hh"
54#include "base/logging.hh"
55#include "base/random.hh"
56#include "base/trace.hh"
57#include "debug/HWPrefetch.hh"
58#include "params/StridePrefetcher.hh"
59
60StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)
61 : QueuedPrefetcher(p),
62 maxConf(p->max_conf),
63 threshConf(p->thresh_conf),
64 minConf(p->min_conf),
65 startConf(p->start_conf),
66 pcTableAssoc(p->table_assoc),
67 pcTableSets(p->table_sets),
68 useMasterId(p->use_master_id),
69 degree(p->degree),
70 pcTable(pcTableAssoc, pcTableSets, name())
71{
72 assert(isPowerOf2(pcTableSets));
73}
74
75StridePrefetcher::StrideEntry**
76StridePrefetcher::PCTable::allocateNewContext(int context)
77{
78 auto res = entries.insert(std::make_pair(context,
79 new StrideEntry*[pcTableSets]));
80 auto it = res.first;
81 chatty_assert(res.second, "Allocating an already created context\n");
82 assert(it->first == context);
83
84 DPRINTF(HWPrefetch, "Adding context %i with stride entries at %p\n",
85 context, it->second);
86
87 StrideEntry** entry = it->second;
88 for (int s = 0; s < pcTableSets; s++) {
89 entry[s] = new StrideEntry[pcTableAssoc];
90 }
91 return entry;
92}
93
94StridePrefetcher::PCTable::~PCTable() {
95 for (auto entry : entries) {
96 for (int s = 0; s < pcTableSets; s++) {
97 delete[] entry.second[s];
98 }
99 delete[] entry.second;
100 }
101}
102
103void
104StridePrefetcher::calculatePrefetch(const PacketPtr &pkt,
105 std::vector<AddrPriority> &addresses)
106{
107 if (!pkt->req->hasPC()) {
108 DPRINTF(HWPrefetch, "Ignoring request with no PC.\n");
109 return;
110 }
111
112 // Get required packet info
113 Addr pkt_addr = pkt->getAddr();
114 Addr pc = pkt->req->getPC();
115 bool is_secure = pkt->isSecure();
116 MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
117
| 1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Steve Reinhardt
42 */
43
44/**
45 * @file
46 * Stride Prefetcher template instantiations.
47 */
48
49#include "mem/cache/prefetch/stride.hh"
50
51#include <cassert>
52
53#include "base/intmath.hh"
54#include "base/logging.hh"
55#include "base/random.hh"
56#include "base/trace.hh"
57#include "debug/HWPrefetch.hh"
58#include "params/StridePrefetcher.hh"
59
60StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)
61 : QueuedPrefetcher(p),
62 maxConf(p->max_conf),
63 threshConf(p->thresh_conf),
64 minConf(p->min_conf),
65 startConf(p->start_conf),
66 pcTableAssoc(p->table_assoc),
67 pcTableSets(p->table_sets),
68 useMasterId(p->use_master_id),
69 degree(p->degree),
70 pcTable(pcTableAssoc, pcTableSets, name())
71{
72 assert(isPowerOf2(pcTableSets));
73}
74
75StridePrefetcher::StrideEntry**
76StridePrefetcher::PCTable::allocateNewContext(int context)
77{
78 auto res = entries.insert(std::make_pair(context,
79 new StrideEntry*[pcTableSets]));
80 auto it = res.first;
81 chatty_assert(res.second, "Allocating an already created context\n");
82 assert(it->first == context);
83
84 DPRINTF(HWPrefetch, "Adding context %i with stride entries at %p\n",
85 context, it->second);
86
87 StrideEntry** entry = it->second;
88 for (int s = 0; s < pcTableSets; s++) {
89 entry[s] = new StrideEntry[pcTableAssoc];
90 }
91 return entry;
92}
93
94StridePrefetcher::PCTable::~PCTable() {
95 for (auto entry : entries) {
96 for (int s = 0; s < pcTableSets; s++) {
97 delete[] entry.second[s];
98 }
99 delete[] entry.second;
100 }
101}
102
103void
104StridePrefetcher::calculatePrefetch(const PacketPtr &pkt,
105 std::vector<AddrPriority> &addresses)
106{
107 if (!pkt->req->hasPC()) {
108 DPRINTF(HWPrefetch, "Ignoring request with no PC.\n");
109 return;
110 }
111
112 // Get required packet info
113 Addr pkt_addr = pkt->getAddr();
114 Addr pc = pkt->req->getPC();
115 bool is_secure = pkt->isSecure();
116 MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
117
|
118 // Lookup pc-based information
119 StrideEntry *entry;
| 118 // Search for entry in the pc table
119 StrideEntry *entry = findEntry(pc, is_secure, master_id);
|
120
| 120
|
121 if (pcTableHit(pc, is_secure, master_id, entry)) {
| 121 if (entry != nullptr) {
|
122 // Hit in table
123 int new_stride = pkt_addr - entry->lastAddr;
124 bool stride_match = (new_stride == entry->stride);
125
126 // Adjust confidence for stride entry
127 if (stride_match && new_stride != 0) {
128 if (entry->confidence < maxConf)
129 entry->confidence++;
130 } else {
131 if (entry->confidence > minConf)
132 entry->confidence--;
133 // If confidence has dropped below the threshold, train new stride
134 if (entry->confidence < threshConf)
135 entry->stride = new_stride;
136 }
137
138 DPRINTF(HWPrefetch, "Hit: PC %x pkt_addr %x (%s) stride %d (%s), "
139 "conf %d\n", pc, pkt_addr, is_secure ? "s" : "ns", new_stride,
140 stride_match ? "match" : "change",
141 entry->confidence);
142
143 entry->lastAddr = pkt_addr;
144
145 // Abort prefetch generation if below confidence threshold
146 if (entry->confidence < threshConf)
147 return;
148
149 // Generate up to degree prefetches
150 for (int d = 1; d <= degree; d++) {
151 // Round strides up to atleast 1 cacheline
152 int prefetch_stride = new_stride;
153 if (abs(new_stride) < blkSize) {
154 prefetch_stride = (new_stride < 0) ? -blkSize : blkSize;
155 }
156
157 Addr new_addr = pkt_addr + d * prefetch_stride;
158 if (samePage(pkt_addr, new_addr)) {
159 DPRINTF(HWPrefetch, "Queuing prefetch to %#x.\n", new_addr);
160 addresses.push_back(AddrPriority(new_addr, 0));
161 } else {
162 // Record the number of page crossing prefetches generated
163 pfSpanPage += degree - d + 1;
164 DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
165 return;
166 }
167 }
168 } else {
169 // Miss in table
170 DPRINTF(HWPrefetch, "Miss: PC %x pkt_addr %x (%s)\n", pc, pkt_addr,
171 is_secure ? "s" : "ns");
172
173 StrideEntry* entry = pcTableVictim(pc, master_id);
174 entry->instAddr = pc;
175 entry->lastAddr = pkt_addr;
176 entry->isSecure= is_secure;
177 entry->stride = 0;
178 entry->confidence = startConf;
179 }
180}
181
182inline Addr
183StridePrefetcher::pcHash(Addr pc) const
184{
185 Addr hash1 = pc >> 1;
186 Addr hash2 = hash1 >> floorLog2(pcTableSets);
187 return (hash1 ^ hash2) & (Addr)(pcTableSets - 1);
188}
189
190inline StridePrefetcher::StrideEntry*
191StridePrefetcher::pcTableVictim(Addr pc, int master_id)
192{
193 // Rand replacement for now
194 int set = pcHash(pc);
195 int way = random_mt.random<int>(0, pcTableAssoc - 1);
196
197 DPRINTF(HWPrefetch, "Victimizing lookup table[%d][%d].\n", set, way);
198 return &pcTable[master_id][set][way];
199}
200
| 122 // Hit in table
123 int new_stride = pkt_addr - entry->lastAddr;
124 bool stride_match = (new_stride == entry->stride);
125
126 // Adjust confidence for stride entry
127 if (stride_match && new_stride != 0) {
128 if (entry->confidence < maxConf)
129 entry->confidence++;
130 } else {
131 if (entry->confidence > minConf)
132 entry->confidence--;
133 // If confidence has dropped below the threshold, train new stride
134 if (entry->confidence < threshConf)
135 entry->stride = new_stride;
136 }
137
138 DPRINTF(HWPrefetch, "Hit: PC %x pkt_addr %x (%s) stride %d (%s), "
139 "conf %d\n", pc, pkt_addr, is_secure ? "s" : "ns", new_stride,
140 stride_match ? "match" : "change",
141 entry->confidence);
142
143 entry->lastAddr = pkt_addr;
144
145 // Abort prefetch generation if below confidence threshold
146 if (entry->confidence < threshConf)
147 return;
148
149 // Generate up to degree prefetches
150 for (int d = 1; d <= degree; d++) {
151 // Round strides up to atleast 1 cacheline
152 int prefetch_stride = new_stride;
153 if (abs(new_stride) < blkSize) {
154 prefetch_stride = (new_stride < 0) ? -blkSize : blkSize;
155 }
156
157 Addr new_addr = pkt_addr + d * prefetch_stride;
158 if (samePage(pkt_addr, new_addr)) {
159 DPRINTF(HWPrefetch, "Queuing prefetch to %#x.\n", new_addr);
160 addresses.push_back(AddrPriority(new_addr, 0));
161 } else {
162 // Record the number of page crossing prefetches generated
163 pfSpanPage += degree - d + 1;
164 DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
165 return;
166 }
167 }
168 } else {
169 // Miss in table
170 DPRINTF(HWPrefetch, "Miss: PC %x pkt_addr %x (%s)\n", pc, pkt_addr,
171 is_secure ? "s" : "ns");
172
173 StrideEntry* entry = pcTableVictim(pc, master_id);
174 entry->instAddr = pc;
175 entry->lastAddr = pkt_addr;
176 entry->isSecure= is_secure;
177 entry->stride = 0;
178 entry->confidence = startConf;
179 }
180}
181
182inline Addr
183StridePrefetcher::pcHash(Addr pc) const
184{
185 Addr hash1 = pc >> 1;
186 Addr hash2 = hash1 >> floorLog2(pcTableSets);
187 return (hash1 ^ hash2) & (Addr)(pcTableSets - 1);
188}
189
190inline StridePrefetcher::StrideEntry*
191StridePrefetcher::pcTableVictim(Addr pc, int master_id)
192{
193 // Rand replacement for now
194 int set = pcHash(pc);
195 int way = random_mt.random<int>(0, pcTableAssoc - 1);
196
197 DPRINTF(HWPrefetch, "Victimizing lookup table[%d][%d].\n", set, way);
198 return &pcTable[master_id][set][way];
199}
200
|
201inline bool
202StridePrefetcher::pcTableHit(Addr pc, bool is_secure, int master_id,
203 StrideEntry* &entry)
| 201inline StridePrefetcher::StrideEntry*
202StridePrefetcher::findEntry(Addr pc, bool is_secure, int master_id)
|
204{
205 int set = pcHash(pc);
206 StrideEntry* set_entries = pcTable[master_id][set];
207 for (int way = 0; way < pcTableAssoc; way++) {
| 203{
204 int set = pcHash(pc);
205 StrideEntry* set_entries = pcTable[master_id][set];
206 for (int way = 0; way < pcTableAssoc; way++) {
|
| 207 StrideEntry* entry = &set_entries[way];
|
208 // Search ways for match
| 208 // Search ways for match
|
209 if (set_entries[way].instAddr == pc &&
210 set_entries[way].isSecure == is_secure) {
| 209 if ((entry->instAddr == pc) && (entry->isSecure == is_secure)) {
|
211 DPRINTF(HWPrefetch, "Lookup hit table[%d][%d].\n", set, way);
| 210 DPRINTF(HWPrefetch, "Lookup hit table[%d][%d].\n", set, way);
|
212 entry = &set_entries[way];
213 return true;
| 211 return entry;
|
214 }
215 }
| 212 }
213 }
|
216 return false;
| 214 return nullptr;
|
217}
218
219StridePrefetcher*
220StridePrefetcherParams::create()
221{
222 return new StridePrefetcher(this);
223}
| 215}
216
217StridePrefetcher*
218StridePrefetcherParams::create()
219{
220 return new StridePrefetcher(this);
221}
|