1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Steve Reinhardt 42 */ 43 44/** 45 * @file 46 * Stride Prefetcher template instantiations. 47 */ 48
| 1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Steve Reinhardt 42 */ 43 44/** 45 * @file 46 * Stride Prefetcher template instantiations. 47 */ 48
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49#include "base/trace.hh"
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50#include "debug/HWPrefetch.hh" 51#include "mem/cache/prefetch/stride.hh" 52
| 49#include "debug/HWPrefetch.hh" 50#include "mem/cache/prefetch/stride.hh" 51
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| 52StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p) 53 : QueuedPrefetcher(p), 54 maxConf(p->max_conf), 55 threshConf(p->thresh_conf), 56 minConf(p->min_conf), 57 startConf(p->start_conf), 58 pcTableAssoc(p->table_assoc), 59 pcTableSets(p->table_sets), 60 useMasterId(p->use_master_id), 61 degree(p->degree) 62{ 63 // Don't consult stride prefetcher on instruction accesses 64 onInst = false; 65 66 assert(isPowerOf2(pcTableSets)); 67 68 for (int c = 0; c < maxContexts; c++) { 69 pcTable[c] = new StrideEntry*[pcTableSets]; 70 for (int s = 0; s < pcTableSets; s++) { 71 pcTable[c][s] = new StrideEntry[pcTableAssoc]; 72 } 73 } 74} 75 76StridePrefetcher::~StridePrefetcher() 77{ 78 for (int c = 0; c < maxContexts; c++) { 79 for (int s = 0; s < pcTableSets; s++) { 80 delete[] pcTable[c][s]; 81 } 82 } 83} 84
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53void
| 85void
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54StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, 55 std::list<Cycles> &delays)
| 86StridePrefetcher::calculatePrefetch(const PacketPtr &pkt, 87 std::vector<Addr> &addresses)
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56{ 57 if (!pkt->req->hasPC()) {
| 88{ 89 if (!pkt->req->hasPC()) {
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58 DPRINTF(HWPrefetch, "ignoring request with no PC");
| 90 DPRINTF(HWPrefetch, "Ignoring request with no PC.\n");
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59 return; 60 } 61
| 91 return; 92 } 93
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62 Addr data_addr = pkt->getAddr();
| 94 // Get required packet info 95 Addr pkt_addr = pkt->getAddr(); 96 Addr pc = pkt->req->getPC();
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63 bool is_secure = pkt->isSecure(); 64 MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
| 97 bool is_secure = pkt->isSecure(); 98 MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
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65 Addr pc = pkt->req->getPC(); 66 assert(master_id < Max_Contexts); 67 std::list<StrideEntry*> &tab = table[master_id];
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68
| 99
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69 // Revert to simple N-block ahead prefetch for instruction fetches 70 if (instTagged && pkt->req->isInstFetch()) { 71 for (int d = 1; d <= degree; d++) { 72 Addr new_addr = data_addr + d * blkSize; 73 if (pageStop && !samePage(data_addr, new_addr)) { 74 // Spanned the page, so now stop 75 pfSpanPage += degree - d + 1; 76 return; 77 } 78 DPRINTF(HWPrefetch, "queuing prefetch to %x @ %d\n", 79 new_addr, latency); 80 addresses.push_back(new_addr); 81 delays.push_back(latency); 82 } 83 return; 84 }
| 100 assert(master_id < maxContexts);
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85
| 101
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86 /* Scan Table for instAddr Match */ 87 std::list<StrideEntry*>::iterator iter; 88 for (iter = tab.begin(); iter != tab.end(); iter++) { 89 // Entries have to match on the security state as well 90 if ((*iter)->instAddr == pc && (*iter)->isSecure == is_secure) 91 break; 92 }
| 102 // Lookup pc-based information 103 StrideEntry *entry;
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93
| 104
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94 if (iter != tab.end()) {
| 105 if(pcTableHit(pc, is_secure, master_id, entry)) {
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95 // Hit in table
| 106 // Hit in table
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| 107 int new_stride = pkt_addr - entry->lastAddr; 108 bool stride_match = (new_stride == entry->stride);
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96
| 109
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97 int new_stride = data_addr - (*iter)->missAddr; 98 bool stride_match = (new_stride == (*iter)->stride); 99
| 110 // Adjust confidence for stride entry
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100 if (stride_match && new_stride != 0) {
| 111 if (stride_match && new_stride != 0) {
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101 (*iter)->tolerance = true; 102 if ((*iter)->confidence < Max_Conf) 103 (*iter)->confidence++;
| 112 if (entry->confidence < maxConf) 113 entry->confidence++;
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104 } else {
| 114 } else {
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105 if (!((*iter)->tolerance)) { 106 (*iter)->stride = new_stride; 107 if ((*iter)->confidence > Min_Conf) 108 (*iter)->confidence = 0; 109 } else { 110 (*iter)->tolerance = false; 111 }
| 115 if (entry->confidence > minConf) 116 entry->confidence--; 117 // If confidence has dropped below the threshold, train new stride 118 if (entry->confidence < threshConf) 119 entry->stride = new_stride;
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112 } 113
| 120 } 121
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114 DPRINTF(HWPrefetch, "hit: PC %x data_addr %x (%s) stride %d (%s), " 115 "conf %d\n", pc, data_addr, is_secure ? "s" : "ns", new_stride,
| 122 DPRINTF(HWPrefetch, "Hit: PC %x pkt_addr %x (%s) stride %d (%s), " 123 "conf %d\n", pc, pkt_addr, is_secure ? "s" : "ns", new_stride,
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116 stride_match ? "match" : "change",
| 124 stride_match ? "match" : "change",
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117 (*iter)->confidence);
| 125 entry->confidence);
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118
| 126
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119 (*iter)->missAddr = data_addr; 120 (*iter)->isSecure = is_secure;
| 127 entry->lastAddr = pkt_addr;
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121
| 128
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122 if ((*iter)->confidence <= 0)
| 129 // Abort prefetch generation if below confidence threshold 130 if (entry->confidence < threshConf)
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123 return; 124
| 131 return; 132
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| 133 // Generate up to degree prefetches
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125 for (int d = 1; d <= degree; d++) {
| 134 for (int d = 1; d <= degree; d++) {
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126 Addr new_addr = data_addr + d * (*iter)->stride; 127 if (pageStop && !samePage(data_addr, new_addr)) { 128 // Spanned the page, so now stop
| 135 // Round strides up to atleast 1 cacheline 136 int prefetch_stride = new_stride; 137 if (abs(new_stride) < blkSize) { 138 prefetch_stride = (new_stride < 0) ? -blkSize : blkSize; 139 } 140 141 Addr new_addr = pkt_addr + d * prefetch_stride; 142 if (samePage(pkt_addr, new_addr)) { 143 DPRINTF(HWPrefetch, "Queuing prefetch to %#x.\n", new_addr); 144 addresses.push_back(new_addr); 145 } else { 146 // Record the number of page crossing prefetches generated
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129 pfSpanPage += degree - d + 1;
| 147 pfSpanPage += degree - d + 1;
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| 148 DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
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130 return;
| 149 return;
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131 } else { 132 DPRINTF(HWPrefetch, " queuing prefetch to %x (%s) @ %d\n", 133 new_addr, is_secure ? "s" : "ns", latency); 134 addresses.push_back(new_addr); 135 delays.push_back(latency);
| |
136 } 137 } 138 } else { 139 // Miss in table
| 150 } 151 } 152 } else { 153 // Miss in table
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140 // Find lowest confidence and replace 141 142 DPRINTF(HWPrefetch, "miss: PC %x data_addr %x (%s)\n", pc, data_addr,
| 154 DPRINTF(HWPrefetch, "Miss: PC %x pkt_addr %x (%s)\n", pc, pkt_addr,
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143 is_secure ? "s" : "ns"); 144
| 155 is_secure ? "s" : "ns"); 156
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145 if (tab.size() >= 256) { //set default table size is 256 146 std::list<StrideEntry*>::iterator min_pos = tab.begin(); 147 int min_conf = (*min_pos)->confidence; 148 for (iter = min_pos, ++iter; iter != tab.end(); ++iter) { 149 if ((*iter)->confidence < min_conf){ 150 min_pos = iter; 151 min_conf = (*iter)->confidence; 152 } 153 } 154 DPRINTF(HWPrefetch, " replacing PC %x (%s)\n", 155 (*min_pos)->instAddr, (*min_pos)->isSecure ? "s" : "ns");
| 157 StrideEntry* entry = pcTableVictim(pc, master_id); 158 entry->instAddr = pc; 159 entry->lastAddr = pkt_addr; 160 entry->isSecure= is_secure; 161 entry->stride = 0; 162 entry->confidence = startConf; 163 } 164}
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156
| 165
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157 // free entry and delete it 158 delete *min_pos; 159 tab.erase(min_pos); 160 }
| 166inline Addr 167StridePrefetcher::pcHash(Addr pc) const 168{ 169 Addr hash1 = pc >> 1; 170 Addr hash2 = hash1 >> floorLog2(pcTableSets); 171 return (hash1 ^ hash2) & (Addr)(pcTableSets - 1); 172}
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161
| 173
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162 StrideEntry *new_entry = new StrideEntry; 163 new_entry->instAddr = pc; 164 new_entry->missAddr = data_addr; 165 new_entry->isSecure = is_secure; 166 new_entry->stride = 0; 167 new_entry->confidence = 0; 168 new_entry->tolerance = false; 169 tab.push_back(new_entry);
| 174inline StridePrefetcher::StrideEntry* 175StridePrefetcher::pcTableVictim(Addr pc, int master_id) 176{ 177 // Rand replacement for now 178 int set = pcHash(pc); 179 int way = rand() % pcTableAssoc; 180 181 DPRINTF(HWPrefetch, "Victimizing lookup table[%d][%d].\n", set, way); 182 return &pcTable[master_id][set][way]; 183} 184 185inline bool 186StridePrefetcher::pcTableHit(Addr pc, bool is_secure, int master_id, 187 StrideEntry* &entry) 188{ 189 int set = pcHash(pc); 190 StrideEntry* set_entries = pcTable[master_id][set]; 191 for (int way = 0; way < pcTableAssoc; way++) { 192 // Search ways for match 193 if (set_entries[way].instAddr == pc && 194 set_entries[way].isSecure == is_secure) { 195 DPRINTF(HWPrefetch, "Lookup hit table[%d][%d].\n", set, way); 196 entry = &set_entries[way]; 197 return true; 198 }
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170 }
| 199 }
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| 200 return false;
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171} 172
| 201} 202
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173
| |
174StridePrefetcher* 175StridePrefetcherParams::create() 176{
| 203StridePrefetcher* 204StridePrefetcherParams::create() 205{
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177 return new StridePrefetcher(this);
| 206 return new StridePrefetcher(this);
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178}
| 207}
|