1/*
| 1/*
|
2 * Copyright (c) 2014 ARM Limited
| 2 * Copyright (c) 2014-2015 ARM Limited
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Mitch Hayenga
38 */
39
40#ifndef __MEM_CACHE_PREFETCH_QUEUED_HH__
41#define __MEM_CACHE_PREFETCH_QUEUED_HH__
42
43#include <list>
44
45#include "mem/cache/prefetch/base.hh"
46#include "params/QueuedPrefetcher.hh"
47
48class QueuedPrefetcher : public BasePrefetcher
49{
50 protected:
51 struct DeferredPacket {
52 Tick tick;
53 PacketPtr pkt;
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Mitch Hayenga
38 */
39
40#ifndef __MEM_CACHE_PREFETCH_QUEUED_HH__
41#define __MEM_CACHE_PREFETCH_QUEUED_HH__
42
43#include <list>
44
45#include "mem/cache/prefetch/base.hh"
46#include "params/QueuedPrefetcher.hh"
47
48class QueuedPrefetcher : public BasePrefetcher
49{
50 protected:
51 struct DeferredPacket {
52 Tick tick;
53 PacketPtr pkt;
|
54 DeferredPacket(Tick t, PacketPtr p) : tick(t), pkt(p) {}
| 54 int32_t priority;
55 DeferredPacket(Tick t, PacketPtr p, int32_t pr) : tick(t), pkt(p),
56 priority(pr) {}
57 bool operator>(const DeferredPacket& that) const
58 {
59 return priority > that.priority;
60 }
61 bool operator<(const DeferredPacket& that) const
62 {
63 return priority < that.priority;
64 }
65 bool operator<=(const DeferredPacket& that) const
66 {
67 return !(*this > that);
68 }
|
55 };
| 69 };
|
| 70 using AddrPriority = std::pair<Addr, int32_t>;
|
56
57 std::list<DeferredPacket> pfq;
58
59 // PARAMETERS
60
61 /** Maximum size of the prefetch queue */
62 const unsigned queueSize;
63
64 /** Cycles after generation when a prefetch can first be issued */
65 const Cycles latency;
66
67 /** Squash queued prefetch if demand access observed */
68 const bool queueSquash;
69
70 /** Filter prefetches if already queued */
71 const bool queueFilter;
72
73 /** Snoop the cache before generating prefetch (cheating basically) */
74 const bool cacheSnoop;
75
76 /** Tag prefetch with PC of generating access? */
77 const bool tagPrefetch;
78
| 71
72 std::list<DeferredPacket> pfq;
73
74 // PARAMETERS
75
76 /** Maximum size of the prefetch queue */
77 const unsigned queueSize;
78
79 /** Cycles after generation when a prefetch can first be issued */
80 const Cycles latency;
81
82 /** Squash queued prefetch if demand access observed */
83 const bool queueSquash;
84
85 /** Filter prefetches if already queued */
86 const bool queueFilter;
87
88 /** Snoop the cache before generating prefetch (cheating basically) */
89 const bool cacheSnoop;
90
91 /** Tag prefetch with PC of generating access? */
92 const bool tagPrefetch;
93
|
79 bool inPrefetch(Addr address, bool is_secure) const;
| 94 using const_iterator = std::list<DeferredPacket>::const_iterator;
95 std::list<DeferredPacket>::const_iterator inPrefetch(Addr address,
96 bool is_secure) const;
97 using iterator = std::list<DeferredPacket>::iterator;
98 std::list<DeferredPacket>::iterator inPrefetch(Addr address,
99 bool is_secure);
|
80
81 // STATS
82 Stats::Scalar pfIdentified;
83 Stats::Scalar pfBufferHit;
84 Stats::Scalar pfInCache;
85 Stats::Scalar pfRemovedFull;
86 Stats::Scalar pfSpanPage;
87
88 public:
89 QueuedPrefetcher(const QueuedPrefetcherParams *p);
90 virtual ~QueuedPrefetcher();
91
92 Tick notify(const PacketPtr &pkt);
| 100
101 // STATS
102 Stats::Scalar pfIdentified;
103 Stats::Scalar pfBufferHit;
104 Stats::Scalar pfInCache;
105 Stats::Scalar pfRemovedFull;
106 Stats::Scalar pfSpanPage;
107
108 public:
109 QueuedPrefetcher(const QueuedPrefetcherParams *p);
110 virtual ~QueuedPrefetcher();
111
112 Tick notify(const PacketPtr &pkt);
|
| 113 PacketPtr insert(AddrPriority& info, bool is_secure);
|
93
94 // Note: This should really be pure virtual, but doesnt go well with params
95 virtual void calculatePrefetch(const PacketPtr &pkt,
| 114
115 // Note: This should really be pure virtual, but doesnt go well with params
116 virtual void calculatePrefetch(const PacketPtr &pkt,
|
96 std::vector &addresses) = 0;
| 117 std::vector<AddrPriority> &addresses) = 0;
|
97 PacketPtr getPacket();
98
99 Tick nextPrefetchReadyTime() const
100 {
101 return pfq.empty() ? MaxTick : pfq.front().tick;
102 }
103
104 void regStats();
105};
106
107#endif //__MEM_CACHE_PREFETCH_QUEUED_HH__
108
| 118 PacketPtr getPacket();
119
120 Tick nextPrefetchReadyTime() const
121 {
122 return pfq.empty() ? MaxTick : pfq.front().tick;
123 }
124
125 void regStats();
126};
127
128#endif //__MEM_CACHE_PREFETCH_QUEUED_HH__
129
|