base.hh (9546:ac0c18d738ce) base.hh (10028:fb8c44de891a)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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132
133 /**
134 * Notify prefetcher of cache access (may be any access or just
135 * misses, depending on cache parameters.)
136 * @retval Time of next prefetch availability, or 0 if none.
137 */
138 Tick notify(PacketPtr &pkt, Tick tick);
139
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 123 unchanged lines hidden (view full) ---

132
133 /**
134 * Notify prefetcher of cache access (may be any access or just
135 * misses, depending on cache parameters.)
136 * @retval Time of next prefetch availability, or 0 if none.
137 */
138 Tick notify(PacketPtr &pkt, Tick tick);
139
140 bool inCache(Addr addr);
140 bool inCache(Addr addr, bool is_secure);
141
141
142 bool inMissQueue(Addr addr);
142 bool inMissQueue(Addr addr, bool is_secure);
143
144 PacketPtr getPacket();
145
146 bool havePending()
147 {
148 return !pf.empty();
149 }
150
151 Tick nextPrefetchReadyTime()
152 {
153 return pf.empty() ? MaxTick : pf.front().tick;
154 }
155
156 virtual void calculatePrefetch(PacketPtr &pkt,
157 std::list<Addr> &addresses,
158 std::list<Cycles> &delays) = 0;
159
143
144 PacketPtr getPacket();
145
146 bool havePending()
147 {
148 return !pf.empty();
149 }
150
151 Tick nextPrefetchReadyTime()
152 {
153 return pf.empty() ? MaxTick : pf.front().tick;
154 }
155
156 virtual void calculatePrefetch(PacketPtr &pkt,
157 std::list<Addr> &addresses,
158 std::list<Cycles> &delays) = 0;
159
160 std::list::iterator inPrefetch(Addr address);
160 std::list<DeferredPacket>::iterator inPrefetch(Addr address, bool is_secure);
161
162 /**
163 * Utility function: are addresses a and b on the same VM page?
164 */
165 bool samePage(Addr a, Addr b);
166 public:
167 const Params*
168 params() const
169 {
170 return dynamic_cast<const Params *>(_params);
171 }
172
173};
174#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
161
162 /**
163 * Utility function: are addresses a and b on the same VM page?
164 */
165 bool samePage(Addr a, Addr b);
166 public:
167 const Params*
168 params() const
169 {
170 return dynamic_cast<const Params *>(_params);
171 }
172
173};
174#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__