base.hh (9288:3d6da8559605) | base.hh (9546:ac0c18d738ce) |
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1/* | 1/* |
2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 34 unchanged lines hidden (view full) --- 44#include "sim/clocked_object.hh" 45 46class BaseCache; 47 48class BasePrefetcher : public ClockedObject 49{ 50 protected: 51 | 14 * Copyright (c) 2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 34 unchanged lines hidden (view full) --- 56#include "sim/clocked_object.hh" 57 58class BaseCache; 59 60class BasePrefetcher : public ClockedObject 61{ 62 protected: 63 |
64 /** A deferred packet, buffered to transmit later. */ 65 class DeferredPacket { 66 public: 67 Tick tick; ///< The tick when the packet is ready to transmit 68 PacketPtr pkt; ///< Pointer to the packet to transmit 69 DeferredPacket(Tick t, PacketPtr p) 70 : tick(t), pkt(p) 71 {} 72 }; 73 |
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52 /** The Prefetch Queue. */ | 74 /** The Prefetch Queue. */ |
53 std::list<PacketPtr> pf; | 75 std::list<DeferredPacket> pf; |
54 55 // PARAMETERS 56 57 /** The number of MSHRs in the Prefetch Queue. */ 58 const unsigned size; 59 60 /** Pointr to the parent cache. */ 61 BaseCache* cache; --- 46 unchanged lines hidden (view full) --- 108 109 void setCache(BaseCache *_cache); 110 111 /** 112 * Notify prefetcher of cache access (may be any access or just 113 * misses, depending on cache parameters.) 114 * @retval Time of next prefetch availability, or 0 if none. 115 */ | 76 77 // PARAMETERS 78 79 /** The number of MSHRs in the Prefetch Queue. */ 80 const unsigned size; 81 82 /** Pointr to the parent cache. */ 83 BaseCache* cache; --- 46 unchanged lines hidden (view full) --- 130 131 void setCache(BaseCache *_cache); 132 133 /** 134 * Notify prefetcher of cache access (may be any access or just 135 * misses, depending on cache parameters.) 136 * @retval Time of next prefetch availability, or 0 if none. 137 */ |
116 Tick notify(PacketPtr &pkt, Tick time); | 138 Tick notify(PacketPtr &pkt, Tick tick); |
117 118 bool inCache(Addr addr); 119 120 bool inMissQueue(Addr addr); 121 122 PacketPtr getPacket(); 123 124 bool havePending() 125 { 126 return !pf.empty(); 127 } 128 129 Tick nextPrefetchReadyTime() 130 { | 139 140 bool inCache(Addr addr); 141 142 bool inMissQueue(Addr addr); 143 144 PacketPtr getPacket(); 145 146 bool havePending() 147 { 148 return !pf.empty(); 149 } 150 151 Tick nextPrefetchReadyTime() 152 { |
131 return pf.empty() ? MaxTick : pf.front()->time; | 153 return pf.empty() ? MaxTick : pf.front().tick; |
132 } 133 134 virtual void calculatePrefetch(PacketPtr &pkt, 135 std::list<Addr> &addresses, 136 std::list<Cycles> &delays) = 0; 137 | 154 } 155 156 virtual void calculatePrefetch(PacketPtr &pkt, 157 std::list<Addr> &addresses, 158 std::list<Cycles> &delays) = 0; 159 |
138 std::list<PacketPtr>::iterator inPrefetch(Addr address); | 160 std::list<DeferredPacket>::iterator inPrefetch(Addr address); |
139 140 /** 141 * Utility function: are addresses a and b on the same VM page? 142 */ 143 bool samePage(Addr a, Addr b); 144 public: 145 const Params* 146 params() const 147 { 148 return dynamic_cast<const Params *>(_params); 149 } 150 151}; 152#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ | 161 162 /** 163 * Utility function: are addresses a and b on the same VM page? 164 */ 165 bool samePage(Addr a, Addr b); 166 public: 167 const Params* 168 params() const 169 { 170 return dynamic_cast<const Params *>(_params); 171 } 172 173}; 174#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ |