base.hh (8832:247fee427324) | base.hh (9288:3d6da8559605) |
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1/* 2 * Copyright (c) 2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ 37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ 38 39#include <list> 40 41#include "base/statistics.hh" 42#include "mem/packet.hh" 43#include "params/BaseCache.hh" | 1/* 2 * Copyright (c) 2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ 37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ 38 39#include <list> 40 41#include "base/statistics.hh" 42#include "mem/packet.hh" 43#include "params/BaseCache.hh" |
44#include "sim/sim_object.hh" | 44#include "sim/clocked_object.hh" |
45 46class BaseCache; 47 | 45 46class BaseCache; 47 |
48class BasePrefetcher : public SimObject | 48class BasePrefetcher : public ClockedObject |
49{ 50 protected: 51 52 /** The Prefetch Queue. */ 53 std::list<PacketPtr> pf; 54 55 // PARAMETERS 56 57 /** The number of MSHRs in the Prefetch Queue. */ 58 const unsigned size; 59 60 /** Pointr to the parent cache. */ 61 BaseCache* cache; 62 63 /** The block size of the parent cache. */ 64 int blkSize; 65 66 /** The latency before a prefetch is issued */ | 49{ 50 protected: 51 52 /** The Prefetch Queue. */ 53 std::list<PacketPtr> pf; 54 55 // PARAMETERS 56 57 /** The number of MSHRs in the Prefetch Queue. */ 58 const unsigned size; 59 60 /** Pointr to the parent cache. */ 61 BaseCache* cache; 62 63 /** The block size of the parent cache. */ 64 int blkSize; 65 66 /** The latency before a prefetch is issued */ |
67 Tick latency; | 67 const Cycles latency; |
68 69 /** The number of prefetches to issue */ 70 unsigned degree; 71 72 /** If patterns should be found per context id */ 73 bool useMasterId; 74 /** Do we prefetch across page boundaries. */ 75 bool pageStop; --- 52 unchanged lines hidden (view full) --- 128 129 Tick nextPrefetchReadyTime() 130 { 131 return pf.empty() ? MaxTick : pf.front()->time; 132 } 133 134 virtual void calculatePrefetch(PacketPtr &pkt, 135 std::list<Addr> &addresses, | 68 69 /** The number of prefetches to issue */ 70 unsigned degree; 71 72 /** If patterns should be found per context id */ 73 bool useMasterId; 74 /** Do we prefetch across page boundaries. */ 75 bool pageStop; --- 52 unchanged lines hidden (view full) --- 128 129 Tick nextPrefetchReadyTime() 130 { 131 return pf.empty() ? MaxTick : pf.front()->time; 132 } 133 134 virtual void calculatePrefetch(PacketPtr &pkt, 135 std::list<Addr> &addresses, |
136 std::list<Tick> &delays) = 0; | 136 std::list<Cycles> &delays) = 0; |
137 138 std::list<PacketPtr>::iterator inPrefetch(Addr address); 139 140 /** 141 * Utility function: are addresses a and b on the same VM page? 142 */ 143 bool samePage(Addr a, Addr b); 144 public: 145 const Params* 146 params() const 147 { 148 return dynamic_cast<const Params *>(_params); 149 } 150 151}; 152#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ | 137 138 std::list<PacketPtr>::iterator inPrefetch(Addr address); 139 140 /** 141 * Utility function: are addresses a and b on the same VM page? 142 */ 143 bool samePage(Addr a, Addr b); 144 public: 145 const Params* 146 params() const 147 { 148 return dynamic_cast<const Params *>(_params); 149 } 150 151}; 152#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ |