base.hh (6665:874f2ee2f115) base.hh (8831:6c08a877af8f)
1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "mem/packet.hh"
43#include "params/BaseCache.hh"
1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 27 unchanged lines hidden (view full) ---

36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "mem/packet.hh"
43#include "params/BaseCache.hh"
44#include "sim/sim_object.hh"
44
45class BaseCache;
46
45
46class BaseCache;
47
47class BasePrefetcher
48class BasePrefetcher : public SimObject
48{
49 protected:
50
51 /** The Prefetch Queue. */
52 std::list<PacketPtr> pf;
53
54 // PARAMETERS
55
56 /** The number of MSHRs in the Prefetch Queue. */
57 const unsigned size;
58
59 /** Pointr to the parent cache. */
60 BaseCache* cache;
61
62 /** The block size of the parent cache. */
63 int blkSize;
64
49{
50 protected:
51
52 /** The Prefetch Queue. */
53 std::list<PacketPtr> pf;
54
55 // PARAMETERS
56
57 /** The number of MSHRs in the Prefetch Queue. */
58 const unsigned size;
59
60 /** Pointr to the parent cache. */
61 BaseCache* cache;
62
63 /** The block size of the parent cache. */
64 int blkSize;
65
66 /** The latency before a prefetch is issued */
67 Tick latency;
68
69 /** The number of prefetches to issue */
70 unsigned degree;
71
72 /** If patterns should be found per context id */
73 bool useContextId;
65 /** Do we prefetch across page boundaries. */
66 bool pageStop;
67
68 /** Do we remove prefetches with later times than a new miss.*/
69 bool serialSquash;
70
71 /** Do we prefetch on only data reads, or on inst reads as well. */
72 bool onlyData;
73
74 /** Do we prefetch across page boundaries. */
75 bool pageStop;
76
77 /** Do we remove prefetches with later times than a new miss.*/
78 bool serialSquash;
79
80 /** Do we prefetch on only data reads, or on inst reads as well. */
81 bool onlyData;
82
74 std::string _name;
75
76 public:
77
78 Stats::Scalar pfIdentified;
79 Stats::Scalar pfMSHRHit;
80 Stats::Scalar pfCacheHit;
81 Stats::Scalar pfBufferHit;
82 Stats::Scalar pfRemovedFull;
83 Stats::Scalar pfRemovedMSHR;
84 Stats::Scalar pfIssued;
85 Stats::Scalar pfSpanPage;
86 Stats::Scalar pfSquashed;
87
83 public:
84
85 Stats::Scalar pfIdentified;
86 Stats::Scalar pfMSHRHit;
87 Stats::Scalar pfCacheHit;
88 Stats::Scalar pfBufferHit;
89 Stats::Scalar pfRemovedFull;
90 Stats::Scalar pfRemovedMSHR;
91 Stats::Scalar pfIssued;
92 Stats::Scalar pfSpanPage;
93 Stats::Scalar pfSquashed;
94
88 void regStats(const std::string &name);
95 void regStats();
89
90 public:
96
97 public:
98 typedef BasePrefetcherParams Params;
99 BasePrefetcher(const Params *p);
91
100
92 BasePrefetcher(const BaseCacheParams *p);
93
94 virtual ~BasePrefetcher() {}
95
101 virtual ~BasePrefetcher() {}
102
96 const std::string name() const { return _name; }
97
98 void setCache(BaseCache *_cache);
99
100 /**
101 * Notify prefetcher of cache access (may be any access or just
102 * misses, depending on cache parameters.)
103 * @retval Time of next prefetch availability, or 0 if none.
104 */
105 Tick notify(PacketPtr &pkt, Tick time);

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125 std::list<Tick> &delays) = 0;
126
127 std::list<PacketPtr>::iterator inPrefetch(Addr address);
128
129 /**
130 * Utility function: are addresses a and b on the same VM page?
131 */
132 bool samePage(Addr a, Addr b);
103 void setCache(BaseCache *_cache);
104
105 /**
106 * Notify prefetcher of cache access (may be any access or just
107 * misses, depending on cache parameters.)
108 * @retval Time of next prefetch availability, or 0 if none.
109 */
110 Tick notify(PacketPtr &pkt, Tick time);

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130 std::list<Tick> &delays) = 0;
131
132 std::list<PacketPtr>::iterator inPrefetch(Addr address);
133
134 /**
135 * Utility function: are addresses a and b on the same VM page?
136 */
137 bool samePage(Addr a, Addr b);
133};
138 public:
139 const Params*
140 params() const
141 {
142 return dynamic_cast<const Params *>(_params);
143 }
134
144
135
145};
136#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
146#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__