base.hh (13416:d90887d0c889) | base.hh (13422:4ec52da74cd5) |
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1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 46 unchanged lines hidden (view full) --- 55#include "base/types.hh" 56#include "mem/packet.hh" 57#include "mem/request.hh" 58#include "sim/clocked_object.hh" 59#include "sim/probe/probe.hh" 60 61class BaseCache; 62struct BasePrefetcherParams; | 1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 46 unchanged lines hidden (view full) --- 55#include "base/types.hh" 56#include "mem/packet.hh" 57#include "mem/request.hh" 58#include "sim/clocked_object.hh" 59#include "sim/probe/probe.hh" 60 61class BaseCache; 62struct BasePrefetcherParams; |
63class System; | |
64 65class BasePrefetcher : public ClockedObject 66{ 67 class PrefetchListener : public ProbeListenerArgBase<PacketPtr> 68 { 69 public: 70 PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm, 71 const std::string &name) --- 13 unchanged lines hidden (view full) --- 85 BaseCache* cache; 86 87 /** The block size of the parent cache. */ 88 unsigned blkSize; 89 90 /** log_2(block size of the parent cache). */ 91 unsigned lBlkSize; 92 | 63 64class BasePrefetcher : public ClockedObject 65{ 66 class PrefetchListener : public ProbeListenerArgBase<PacketPtr> 67 { 68 public: 69 PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm, 70 const std::string &name) --- 13 unchanged lines hidden (view full) --- 84 BaseCache* cache; 85 86 /** The block size of the parent cache. */ 87 unsigned blkSize; 88 89 /** log_2(block size of the parent cache). */ 90 unsigned lBlkSize; 91 |
93 /** System we belong to */ 94 System* system; 95 | |
96 /** Only consult prefetcher on cache misses? */ | 92 /** Only consult prefetcher on cache misses? */ |
97 bool onMiss; | 93 const bool onMiss; |
98 99 /** Consult prefetcher on reads? */ | 94 95 /** Consult prefetcher on reads? */ |
100 bool onRead; | 96 const bool onRead; |
101 102 /** Consult prefetcher on reads? */ | 97 98 /** Consult prefetcher on reads? */ |
103 bool onWrite; | 99 const bool onWrite; |
104 105 /** Consult prefetcher on data accesses? */ | 100 101 /** Consult prefetcher on data accesses? */ |
106 bool onData; | 102 const bool onData; |
107 108 /** Consult prefetcher on instruction accesses? */ | 103 104 /** Consult prefetcher on instruction accesses? */ |
109 bool onInst; | 105 const bool onInst; |
110 111 /** Request id for prefetches */ | 106 107 /** Request id for prefetches */ |
112 MasterID masterId; | 108 const MasterID masterId; |
113 114 const Addr pageBytes; 115 116 /** Prefetch on every access, not just misses */ 117 const bool prefetchOnAccess; 118 119 /** Determine if this access should be observed */ 120 bool observeAccess(const PacketPtr &pkt) const; --- 21 unchanged lines hidden (view full) --- 142 Stats::Scalar pfIssued; 143 144 public: 145 146 BasePrefetcher(const BasePrefetcherParams *p); 147 148 virtual ~BasePrefetcher() {} 149 | 109 110 const Addr pageBytes; 111 112 /** Prefetch on every access, not just misses */ 113 const bool prefetchOnAccess; 114 115 /** Determine if this access should be observed */ 116 bool observeAccess(const PacketPtr &pkt) const; --- 21 unchanged lines hidden (view full) --- 138 Stats::Scalar pfIssued; 139 140 public: 141 142 BasePrefetcher(const BasePrefetcherParams *p); 143 144 virtual ~BasePrefetcher() {} 145 |
150 virtual void setCache(BaseCache *_cache); | 146 void setCache(BaseCache *_cache); |
151 152 /** 153 * Notify prefetcher of cache access (may be any access or just 154 * misses, depending on cache parameters.) 155 */ 156 virtual void notify(const PacketPtr &pkt) = 0; 157 158 virtual PacketPtr getPacket() = 0; 159 160 virtual Tick nextPrefetchReadyTime() const = 0; 161 | 147 148 /** 149 * Notify prefetcher of cache access (may be any access or just 150 * misses, depending on cache parameters.) 151 */ 152 virtual void notify(const PacketPtr &pkt) = 0; 153 154 virtual PacketPtr getPacket() = 0; 155 156 virtual Tick nextPrefetchReadyTime() const = 0; 157 |
162 virtual void regStats(); | 158 /** 159 * Register local statistics. 160 */ 161 void regStats() override; |
163 164 /** 165 * Register probe points for this object. 166 */ 167 void regProbeListeners() override; 168 169 /** 170 * Process a notification event from the ProbeListener. --- 12 unchanged lines hidden --- | 162 163 /** 164 * Register probe points for this object. 165 */ 166 void regProbeListeners() override; 167 168 /** 169 * Process a notification event from the ProbeListener. --- 12 unchanged lines hidden --- |