base.hh (12727:56c23b54bcb1) | base.hh (13416:d90887d0c889) |
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1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 42 unchanged lines hidden (view full) --- 51 52#include <cstdint> 53 54#include "base/statistics.hh" 55#include "base/types.hh" 56#include "mem/packet.hh" 57#include "mem/request.hh" 58#include "sim/clocked_object.hh" | 1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 42 unchanged lines hidden (view full) --- 51 52#include <cstdint> 53 54#include "base/statistics.hh" 55#include "base/types.hh" 56#include "mem/packet.hh" 57#include "mem/request.hh" 58#include "sim/clocked_object.hh" |
59#include "sim/probe/probe.hh" |
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59 60class BaseCache; 61struct BasePrefetcherParams; 62class System; 63 64class BasePrefetcher : public ClockedObject 65{ | 60 61class BaseCache; 62struct BasePrefetcherParams; 63class System; 64 65class BasePrefetcher : public ClockedObject 66{ |
67 class PrefetchListener : public ProbeListenerArgBase<PacketPtr> 68 { 69 public: 70 PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm, 71 const std::string &name) 72 : ProbeListenerArgBase(pm, name), 73 parent(_parent) {} 74 void notify(const PacketPtr &pkt) override; 75 protected: 76 BasePrefetcher &parent; 77 }; 78 79 std::vector<PrefetchListener *> listeners; |
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66 protected: 67 68 // PARAMETERS 69 70 /** Pointr to the parent cache. */ 71 BaseCache* cache; 72 73 /** The block size of the parent cache. */ --- 20 unchanged lines hidden (view full) --- 94 /** Consult prefetcher on instruction accesses? */ 95 bool onInst; 96 97 /** Request id for prefetches */ 98 MasterID masterId; 99 100 const Addr pageBytes; 101 | 80 protected: 81 82 // PARAMETERS 83 84 /** Pointr to the parent cache. */ 85 BaseCache* cache; 86 87 /** The block size of the parent cache. */ --- 20 unchanged lines hidden (view full) --- 108 /** Consult prefetcher on instruction accesses? */ 109 bool onInst; 110 111 /** Request id for prefetches */ 112 MasterID masterId; 113 114 const Addr pageBytes; 115 |
116 /** Prefetch on every access, not just misses */ 117 const bool prefetchOnAccess; 118 |
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102 /** Determine if this access should be observed */ 103 bool observeAccess(const PacketPtr &pkt) const; 104 105 /** Determine if address is in cache */ 106 bool inCache(Addr addr, bool is_secure) const; 107 108 /** Determine if address is in cache miss queue */ 109 bool inMissQueue(Addr addr, bool is_secure) const; --- 20 unchanged lines hidden (view full) --- 130 131 virtual ~BasePrefetcher() {} 132 133 virtual void setCache(BaseCache *_cache); 134 135 /** 136 * Notify prefetcher of cache access (may be any access or just 137 * misses, depending on cache parameters.) | 119 /** Determine if this access should be observed */ 120 bool observeAccess(const PacketPtr &pkt) const; 121 122 /** Determine if address is in cache */ 123 bool inCache(Addr addr, bool is_secure) const; 124 125 /** Determine if address is in cache miss queue */ 126 bool inMissQueue(Addr addr, bool is_secure) const; --- 20 unchanged lines hidden (view full) --- 147 148 virtual ~BasePrefetcher() {} 149 150 virtual void setCache(BaseCache *_cache); 151 152 /** 153 * Notify prefetcher of cache access (may be any access or just 154 * misses, depending on cache parameters.) |
138 * @retval Time of next prefetch availability, or MaxTick if none. | |
139 */ | 155 */ |
140 virtual Tick notify(const PacketPtr &pkt) = 0; | 156 virtual void notify(const PacketPtr &pkt) = 0; |
141 142 virtual PacketPtr getPacket() = 0; 143 144 virtual Tick nextPrefetchReadyTime() const = 0; 145 146 virtual void regStats(); | 157 158 virtual PacketPtr getPacket() = 0; 159 160 virtual Tick nextPrefetchReadyTime() const = 0; 161 162 virtual void regStats(); |
163 164 /** 165 * Register probe points for this object. 166 */ 167 void regProbeListeners() override; 168 169 /** 170 * Process a notification event from the ProbeListener. 171 * @param pkt The memory request causing the event 172 */ 173 void probeNotify(const PacketPtr &pkt); 174 175 /** 176 * Add a SimObject and a probe name to listen events from 177 * @param obj The SimObject pointer to listen from 178 * @param name The probe name 179 */ 180 void addEventProbe(SimObject *obj, const char *name); |
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147}; 148#endif //__MEM_CACHE_PREFETCH_BASE_HH__ | 181}; 182#endif //__MEM_CACHE_PREFETCH_BASE_HH__ |