base.hh (10028:fb8c44de891a) | base.hh (10052:5bb8e054456b) |
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1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 75 unchanged lines hidden (view full) --- 84 85 /** The block size of the parent cache. */ 86 int blkSize; 87 88 /** The latency before a prefetch is issued */ 89 const Cycles latency; 90 91 /** The number of prefetches to issue */ | 1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 75 unchanged lines hidden (view full) --- 84 85 /** The block size of the parent cache. */ 86 int blkSize; 87 88 /** The latency before a prefetch is issued */ 89 const Cycles latency; 90 91 /** The number of prefetches to issue */ |
92 unsigned degree; | 92 const unsigned degree; |
93 94 /** If patterns should be found per context id */ | 93 94 /** If patterns should be found per context id */ |
95 bool useMasterId; | 95 const bool useMasterId; |
96 /** Do we prefetch across page boundaries. */ | 96 /** Do we prefetch across page boundaries. */ |
97 bool pageStop; | 97 const bool pageStop; |
98 99 /** Do we remove prefetches with later times than a new miss.*/ | 98 99 /** Do we remove prefetches with later times than a new miss.*/ |
100 bool serialSquash; | 100 const bool serialSquash; |
101 102 /** Do we prefetch on only data reads, or on inst reads as well. */ | 101 102 /** Do we prefetch on only data reads, or on inst reads as well. */ |
103 bool onlyData; | 103 const bool onlyData; |
104 | 104 |
105 /** Do we trigger/train prefetch on cache misses only, or all accesses. */ 106 const bool onMissOnly; 107 108 /** Do we trigger/train prefetch on reads only, or all accesses. */ 109 const bool onReadOnly; 110 111 /** Do we tag prefetch's with PC addresses, allowing lower pc-based 112 prefetchers to prefetch on prefetch requests */ 113 const bool onPrefetch; 114 |
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105 /** System we belong to */ 106 System* system; 107 108 /** Request id for prefetches */ 109 MasterID masterId; 110 111 public: 112 --- 62 unchanged lines hidden --- | 115 /** System we belong to */ 116 System* system; 117 118 /** Request id for prefetches */ 119 MasterID masterId; 120 121 public: 122 --- 62 unchanged lines hidden --- |