1/* 2 * Copyright (c) 2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 59 unchanged lines hidden (view full) --- 68 /** Do we remove prefetches with later times than a new miss.*/ 69 bool serialSquash; 70 71 /** Do we check if it is in the cache when inserting into buffer, 72 or removing.*/ 73 bool cacheCheckPush; 74 75 /** Do we prefetch on only data reads, or on inst reads as well. */ |
76 bool onlyData; |
77 |
78 std::string _name; 79 |
80 public: 81 82 Stats::Scalar<> pfIdentified; 83 Stats::Scalar<> pfMSHRHit; 84 Stats::Scalar<> pfCacheHit; 85 Stats::Scalar<> pfBufferHit; 86 Stats::Scalar<> pfRemovedFull; 87 Stats::Scalar<> pfRemovedMSHR; 88 Stats::Scalar<> pfIssued; 89 Stats::Scalar<> pfSpanPage; 90 Stats::Scalar<> pfSquashed; 91 92 void regStats(const std::string &name); 93 94 public: |
95 |
96 BasePrefetcher(const BaseCacheParams *p); 97 98 virtual ~BasePrefetcher() {} 99 |
100 const std::string name() const { return _name; } 101 |
102 void setCache(BaseCache *_cache); 103 |
104 /** 105 * Notify prefetcher of cache access (may be any access or just 106 * misses, depending on cache parameters.) 107 * @retval Time of next prefetch availability, or 0 if none. 108 */ 109 Tick notify(PacketPtr &pkt, Tick time); |
110 111 bool inCache(Addr addr); 112 113 bool inMissQueue(Addr addr); 114 115 PacketPtr getPacket(); 116 117 bool havePending() 118 { 119 return !pf.empty(); 120 } 121 |
122 Tick nextPrefetchReadyTime() 123 { 124 return pf.empty() ? MaxTick : pf.front()->time; 125 } 126 |
127 virtual void calculatePrefetch(PacketPtr &pkt, 128 std::list<Addr> &addresses, 129 std::list<Tick> &delays) = 0; 130 131 std::list<PacketPtr>::iterator inPrefetch(Addr address); |
132 133 /** 134 * Utility function: are addresses a and b on the same VM page? 135 */ 136 bool samePage(Addr a, Addr b); |
137}; 138 139 140#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ |