1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Miss and writeback queue declarations.
34 */
35
36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "mem/packet.hh"
43#include "params/BaseCache.hh"
44#include "sim/sim_object.hh"
45
46class BaseCache;
47
48class BasePrefetcher : public SimObject
49{
50 protected:
51
52 /** The Prefetch Queue. */
53 std::list<PacketPtr> pf;
54
55 // PARAMETERS
56
57 /** The number of MSHRs in the Prefetch Queue. */
58 const unsigned size;
59
60 /** Pointr to the parent cache. */
61 BaseCache* cache;
62
63 /** The block size of the parent cache. */
64 int blkSize;
65
66 /** The latency before a prefetch is issued */
67 Tick latency;
68
69 /** The number of prefetches to issue */
70 unsigned degree;
71
72 /** If patterns should be found per context id */
| 1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Miss and writeback queue declarations.
34 */
35
36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "mem/packet.hh"
43#include "params/BaseCache.hh"
44#include "sim/sim_object.hh"
45
46class BaseCache;
47
48class BasePrefetcher : public SimObject
49{
50 protected:
51
52 /** The Prefetch Queue. */
53 std::list<PacketPtr> pf;
54
55 // PARAMETERS
56
57 /** The number of MSHRs in the Prefetch Queue. */
58 const unsigned size;
59
60 /** Pointr to the parent cache. */
61 BaseCache* cache;
62
63 /** The block size of the parent cache. */
64 int blkSize;
65
66 /** The latency before a prefetch is issued */
67 Tick latency;
68
69 /** The number of prefetches to issue */
70 unsigned degree;
71
72 /** If patterns should be found per context id */
|
74 /** Do we prefetch across page boundaries. */
75 bool pageStop;
76
77 /** Do we remove prefetches with later times than a new miss.*/
78 bool serialSquash;
79
80 /** Do we prefetch on only data reads, or on inst reads as well. */
81 bool onlyData;
82
| 74 /** Do we prefetch across page boundaries. */
75 bool pageStop;
76
77 /** Do we remove prefetches with later times than a new miss.*/
78 bool serialSquash;
79
80 /** Do we prefetch on only data reads, or on inst reads as well. */
81 bool onlyData;
82
|
83 public:
84
85 Stats::Scalar pfIdentified;
86 Stats::Scalar pfMSHRHit;
87 Stats::Scalar pfCacheHit;
88 Stats::Scalar pfBufferHit;
89 Stats::Scalar pfRemovedFull;
90 Stats::Scalar pfRemovedMSHR;
91 Stats::Scalar pfIssued;
92 Stats::Scalar pfSpanPage;
93 Stats::Scalar pfSquashed;
94
95 void regStats();
96
97 public:
98 typedef BasePrefetcherParams Params;
99 BasePrefetcher(const Params *p);
100
101 virtual ~BasePrefetcher() {}
102
103 void setCache(BaseCache *_cache);
104
105 /**
106 * Notify prefetcher of cache access (may be any access or just
107 * misses, depending on cache parameters.)
108 * @retval Time of next prefetch availability, or 0 if none.
109 */
110 Tick notify(PacketPtr &pkt, Tick time);
111
112 bool inCache(Addr addr);
113
114 bool inMissQueue(Addr addr);
115
116 PacketPtr getPacket();
117
118 bool havePending()
119 {
120 return !pf.empty();
121 }
122
123 Tick nextPrefetchReadyTime()
124 {
125 return pf.empty() ? MaxTick : pf.front()->time;
126 }
127
128 virtual void calculatePrefetch(PacketPtr &pkt,
129 std::list<Addr> &addresses,
130 std::list<Tick> &delays) = 0;
131
132 std::list<PacketPtr>::iterator inPrefetch(Addr address);
133
134 /**
135 * Utility function: are addresses a and b on the same VM page?
136 */
137 bool samePage(Addr a, Addr b);
138 public:
139 const Params*
140 params() const
141 {
142 return dynamic_cast<const Params *>(_params);
143 }
144
145};
146#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
| 89 public:
90
91 Stats::Scalar pfIdentified;
92 Stats::Scalar pfMSHRHit;
93 Stats::Scalar pfCacheHit;
94 Stats::Scalar pfBufferHit;
95 Stats::Scalar pfRemovedFull;
96 Stats::Scalar pfRemovedMSHR;
97 Stats::Scalar pfIssued;
98 Stats::Scalar pfSpanPage;
99 Stats::Scalar pfSquashed;
100
101 void regStats();
102
103 public:
104 typedef BasePrefetcherParams Params;
105 BasePrefetcher(const Params *p);
106
107 virtual ~BasePrefetcher() {}
108
109 void setCache(BaseCache *_cache);
110
111 /**
112 * Notify prefetcher of cache access (may be any access or just
113 * misses, depending on cache parameters.)
114 * @retval Time of next prefetch availability, or 0 if none.
115 */
116 Tick notify(PacketPtr &pkt, Tick time);
117
118 bool inCache(Addr addr);
119
120 bool inMissQueue(Addr addr);
121
122 PacketPtr getPacket();
123
124 bool havePending()
125 {
126 return !pf.empty();
127 }
128
129 Tick nextPrefetchReadyTime()
130 {
131 return pf.empty() ? MaxTick : pf.front()->time;
132 }
133
134 virtual void calculatePrefetch(PacketPtr &pkt,
135 std::list<Addr> &addresses,
136 std::list<Tick> &delays) = 0;
137
138 std::list<PacketPtr>::iterator inPrefetch(Addr address);
139
140 /**
141 * Utility function: are addresses a and b on the same VM page?
142 */
143 bool samePage(Addr a, Addr b);
144 public:
145 const Params*
146 params() const
147 {
148 return dynamic_cast<const Params *>(_params);
149 }
150
151};
152#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
|