1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Miss and writeback queue declarations.
34 */
35
36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "mem/packet.hh"
43#include "params/BaseCache.hh"
44
45class BaseCache;
46
47class BasePrefetcher
48{
49 protected:
50
51 /** The Prefetch Queue. */
52 std::list<PacketPtr> pf;
53
54 // PARAMETERS
55
56 /** The number of MSHRs in the Prefetch Queue. */
| 1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Miss and writeback queue declarations.
34 */
35
36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "mem/packet.hh"
43#include "params/BaseCache.hh"
44
45class BaseCache;
46
47class BasePrefetcher
48{
49 protected:
50
51 /** The Prefetch Queue. */
52 std::list<PacketPtr> pf;
53
54 // PARAMETERS
55
56 /** The number of MSHRs in the Prefetch Queue. */
|
58
59 /** Pointr to the parent cache. */
60 BaseCache* cache;
61
62 /** The block size of the parent cache. */
63 int blkSize;
64
65 /** Do we prefetch across page boundaries. */
66 bool pageStop;
67
68 /** Do we remove prefetches with later times than a new miss.*/
69 bool serialSquash;
70
71 /** Do we check if it is in the cache when inserting into buffer,
72 or removing.*/
73 bool cacheCheckPush;
74
75 /** Do we prefetch on only data reads, or on inst reads as well. */
76 bool onlyData;
77
78 std::string _name;
79
80 public:
81
82 Stats::Scalar pfIdentified;
83 Stats::Scalar pfMSHRHit;
84 Stats::Scalar pfCacheHit;
85 Stats::Scalar pfBufferHit;
86 Stats::Scalar pfRemovedFull;
87 Stats::Scalar pfRemovedMSHR;
88 Stats::Scalar pfIssued;
89 Stats::Scalar pfSpanPage;
90 Stats::Scalar pfSquashed;
91
92 void regStats(const std::string &name);
93
94 public:
95
96 BasePrefetcher(const BaseCacheParams *p);
97
98 virtual ~BasePrefetcher() {}
99
100 const std::string name() const { return _name; }
101
102 void setCache(BaseCache *_cache);
103
104 /**
105 * Notify prefetcher of cache access (may be any access or just
106 * misses, depending on cache parameters.)
107 * @retval Time of next prefetch availability, or 0 if none.
108 */
109 Tick notify(PacketPtr &pkt, Tick time);
110
111 bool inCache(Addr addr);
112
113 bool inMissQueue(Addr addr);
114
115 PacketPtr getPacket();
116
117 bool havePending()
118 {
119 return !pf.empty();
120 }
121
122 Tick nextPrefetchReadyTime()
123 {
124 return pf.empty() ? MaxTick : pf.front()->time;
125 }
126
127 virtual void calculatePrefetch(PacketPtr &pkt,
128 std::list<Addr> &addresses,
129 std::list<Tick> &delays) = 0;
130
131 std::list<PacketPtr>::iterator inPrefetch(Addr address);
132
133 /**
134 * Utility function: are addresses a and b on the same VM page?
135 */
136 bool samePage(Addr a, Addr b);
137};
138
139
140#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
| 58
59 /** Pointr to the parent cache. */
60 BaseCache* cache;
61
62 /** The block size of the parent cache. */
63 int blkSize;
64
65 /** Do we prefetch across page boundaries. */
66 bool pageStop;
67
68 /** Do we remove prefetches with later times than a new miss.*/
69 bool serialSquash;
70
71 /** Do we check if it is in the cache when inserting into buffer,
72 or removing.*/
73 bool cacheCheckPush;
74
75 /** Do we prefetch on only data reads, or on inst reads as well. */
76 bool onlyData;
77
78 std::string _name;
79
80 public:
81
82 Stats::Scalar pfIdentified;
83 Stats::Scalar pfMSHRHit;
84 Stats::Scalar pfCacheHit;
85 Stats::Scalar pfBufferHit;
86 Stats::Scalar pfRemovedFull;
87 Stats::Scalar pfRemovedMSHR;
88 Stats::Scalar pfIssued;
89 Stats::Scalar pfSpanPage;
90 Stats::Scalar pfSquashed;
91
92 void regStats(const std::string &name);
93
94 public:
95
96 BasePrefetcher(const BaseCacheParams *p);
97
98 virtual ~BasePrefetcher() {}
99
100 const std::string name() const { return _name; }
101
102 void setCache(BaseCache *_cache);
103
104 /**
105 * Notify prefetcher of cache access (may be any access or just
106 * misses, depending on cache parameters.)
107 * @retval Time of next prefetch availability, or 0 if none.
108 */
109 Tick notify(PacketPtr &pkt, Tick time);
110
111 bool inCache(Addr addr);
112
113 bool inMissQueue(Addr addr);
114
115 PacketPtr getPacket();
116
117 bool havePending()
118 {
119 return !pf.empty();
120 }
121
122 Tick nextPrefetchReadyTime()
123 {
124 return pf.empty() ? MaxTick : pf.front()->time;
125 }
126
127 virtual void calculatePrefetch(PacketPtr &pkt,
128 std::list<Addr> &addresses,
129 std::list<Tick> &delays) = 0;
130
131 std::list<PacketPtr>::iterator inPrefetch(Addr address);
132
133 /**
134 * Utility function: are addresses a and b on the same VM page?
135 */
136 bool samePage(Addr a, Addr b);
137};
138
139
140#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
|