1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Miss and writeback queue declarations.
47 */
48
49#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
50#define __MEM_CACHE_PREFETCH_BASE_HH__
51
52#include <cstdint>
53
54#include "base/statistics.hh"
55#include "base/types.hh"
56#include "mem/packet.hh"
57#include "mem/request.hh"
58#include "sim/clocked_object.hh"
59#include "sim/probe/probe.hh"
60
61class BaseCache;
62struct BasePrefetcherParams;
63class System;
64
65class BasePrefetcher : public ClockedObject
66{
67 class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
68 {
69 public:
70 PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm,
71 const std::string &name)
72 : ProbeListenerArgBase(pm, name),
73 parent(_parent) {}
74 void notify(const PacketPtr &pkt) override;
75 protected:
76 BasePrefetcher &parent;
77 };
78
79 std::vector<PrefetchListener *> listeners;
80 protected:
81
82 // PARAMETERS
83
84 /** Pointr to the parent cache. */
85 BaseCache* cache;
86
87 /** The block size of the parent cache. */
88 unsigned blkSize;
89
90 /** log_2(block size of the parent cache). */
91 unsigned lBlkSize;
92
93 /** System we belong to */
94 System* system;
95
96 /** Only consult prefetcher on cache misses? */
97 bool onMiss;
98
99 /** Consult prefetcher on reads? */
100 bool onRead;
101
102 /** Consult prefetcher on reads? */
103 bool onWrite;
104
105 /** Consult prefetcher on data accesses? */
106 bool onData;
107
108 /** Consult prefetcher on instruction accesses? */
109 bool onInst;
110
111 /** Request id for prefetches */
112 MasterID masterId;
113
114 const Addr pageBytes;
115
116 /** Prefetch on every access, not just misses */
117 const bool prefetchOnAccess;
118
119 /** Determine if this access should be observed */
120 bool observeAccess(const PacketPtr &pkt) const;
121
122 /** Determine if address is in cache */
123 bool inCache(Addr addr, bool is_secure) const;
124
125 /** Determine if address is in cache miss queue */
126 bool inMissQueue(Addr addr, bool is_secure) const;
127
128 /** Determine if addresses are on the same page */
129 bool samePage(Addr a, Addr b) const;
130 /** Determine the address of the block in which a lays */
131 Addr blockAddress(Addr a) const;
132 /** Determine the address of a at block granularity */
133 Addr blockIndex(Addr a) const;
134 /** Determine the address of the page in which a lays */
135 Addr pageAddress(Addr a) const;
136 /** Determine the page-offset of a */
137 Addr pageOffset(Addr a) const;
138 /** Build the address of the i-th block inside the page */
139 Addr pageIthBlockAddress(Addr page, uint32_t i) const;
140
141
142 Stats::Scalar pfIssued;
143
144 public:
145
146 BasePrefetcher(const BasePrefetcherParams *p);
147
148 virtual ~BasePrefetcher() {}
149
150 virtual void setCache(BaseCache *_cache);
151
152 /**
153 * Notify prefetcher of cache access (may be any access or just
154 * misses, depending on cache parameters.)
155 */
156 virtual void notify(const PacketPtr &pkt) = 0;
157
158 virtual PacketPtr getPacket() = 0;
159
160 virtual Tick nextPrefetchReadyTime() const = 0;
161
162 virtual void regStats();
163
164 /**
165 * Register probe points for this object.
166 */
167 void regProbeListeners() override;
168
169 /**
170 * Process a notification event from the ProbeListener.
171 * @param pkt The memory request causing the event
172 */
173 void probeNotify(const PacketPtr &pkt);
174
175 /**
176 * Add a SimObject and a probe name to listen events from
177 * @param obj The SimObject pointer to listen from
178 * @param name The probe name
179 */
180 void addEventProbe(SimObject *obj, const char *name);
181};
182#endif //__MEM_CACHE_PREFETCH_BASE_HH__