1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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68 /** Do we remove prefetches with later times than a new miss.*/
69 bool serialSquash;
70
71 /** Do we check if it is in the cache when inserting into buffer,
72 or removing.*/
73 bool cacheCheckPush;
74
75 /** Do we prefetch on only data reads, or on inst reads as well. */
76 bool only_data;
77
78 public:
79
80 Stats::Scalar<> pfIdentified;
81 Stats::Scalar<> pfMSHRHit;
82 Stats::Scalar<> pfCacheHit;
83 Stats::Scalar<> pfBufferHit;
84 Stats::Scalar<> pfRemovedFull;
85 Stats::Scalar<> pfRemovedMSHR;
86 Stats::Scalar<> pfIssued;
87 Stats::Scalar<> pfSpanPage;
88 Stats::Scalar<> pfSquashed;
89
90 void regStats(const std::string &name);
91
92 public:
93 BasePrefetcher(const BaseCacheParams *p);
94
95 virtual ~BasePrefetcher() {}
96
97 void setCache(BaseCache *_cache);
98
99 void handleMiss(PacketPtr &pkt, Tick time);
100
101 bool inCache(Addr addr);
102
103 bool inMissQueue(Addr addr);
104
105 PacketPtr getPacket();
106
107 bool havePending()
108 {
109 return !pf.empty();
110 }
111
112 virtual void calculatePrefetch(PacketPtr &pkt,
113 std::list<Addr> &addresses,
114 std::list<Tick> &delays) = 0;
115
116 std::list<PacketPtr>::iterator inPrefetch(Addr address);
117};
118
119
120#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__