base.cc (8949:3fa1ee293096) base.cc (8991:69fad6658160)
1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 168 unchanged lines hidden (view full) ---

177 // Check if miss is in pfq, if so remove it
178 std::list<PacketPtr>::iterator iter = inPrefetch(blk_addr);
179 if (iter != pf.end()) {
180 DPRINTF(HWPrefetch, "Saw a miss to a queued prefetch addr: "
181 "0x%x, removing it\n", blk_addr);
182 pfRemovedMSHR++;
183 delete (*iter)->req;
184 delete (*iter);
1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 168 unchanged lines hidden (view full) ---

177 // Check if miss is in pfq, if so remove it
178 std::list<PacketPtr>::iterator iter = inPrefetch(blk_addr);
179 if (iter != pf.end()) {
180 DPRINTF(HWPrefetch, "Saw a miss to a queued prefetch addr: "
181 "0x%x, removing it\n", blk_addr);
182 pfRemovedMSHR++;
183 delete (*iter)->req;
184 delete (*iter);
185 pf.erase(iter);
185 iter = pf.erase(iter);
186 if (pf.empty())
187 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
188 }
189
190 // Remove anything in queue with delay older than time
191 // since everything is inserted in time order, start from end
192 // and work until pf.empty() or time is earlier
193 // This is done to emulate Aborting the previous work on a new miss
194 // Needed for serial calculators like GHB
195 if (serialSquash) {
196 iter = pf.end();
186 if (pf.empty())
187 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
188 }
189
190 // Remove anything in queue with delay older than time
191 // since everything is inserted in time order, start from end
192 // and work until pf.empty() or time is earlier
193 // This is done to emulate Aborting the previous work on a new miss
194 // Needed for serial calculators like GHB
195 if (serialSquash) {
196 iter = pf.end();
197 iter--;
197 if (iter != pf.begin())
198 iter--;
198 while (!pf.empty() && ((*iter)->time >= time)) {
199 pfSquashed++;
200 DPRINTF(HWPrefetch, "Squashing old prefetch addr: 0x%x\n",
201 (*iter)->getAddr());
202 delete (*iter)->req;
203 delete (*iter);
199 while (!pf.empty() && ((*iter)->time >= time)) {
200 pfSquashed++;
201 DPRINTF(HWPrefetch, "Squashing old prefetch addr: 0x%x\n",
202 (*iter)->getAddr());
203 delete (*iter)->req;
204 delete (*iter);
204 pf.erase(iter);
205 iter--;
205 iter = pf.erase(iter);
206 if (iter != pf.begin())
207 iter--;
206 }
207 if (pf.empty())
208 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
209 }
210
211
212 std::list<Addr> addresses;
213 std::list<Tick> delays;

--- 68 unchanged lines hidden --- 		208 }
209 if (pf.empty())
210 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
211 }
212
213
214 std::list<Addr> addresses;
215 std::list<Tick> delays;

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