base.cc (5714:76abee886def) base.cc (5875:d82be3235ab4)
1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Hardware Prefetcher Definition.
34 */
35
1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 19 unchanged lines hidden (view full) ---

28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Hardware Prefetcher Definition.
34 */
35
36#include "arch/isa_traits.hh"
36#include "base/trace.hh"
37#include "mem/cache/base.hh"
38#include "mem/cache/prefetch/base.hh"
39#include "mem/request.hh"
40#include <list>
41
42BasePrefetcher::BasePrefetcher(const BaseCacheParams *p)
43 : size(p->prefetcher_size), pageStop(!p->prefetch_past_page),
44 serialSquash(p->prefetch_serial_squash),
45 cacheCheckPush(p->prefetch_cache_check_push),
37#include "base/trace.hh"
38#include "mem/cache/base.hh"
39#include "mem/cache/prefetch/base.hh"
40#include "mem/request.hh"
41#include <list>
42
43BasePrefetcher::BasePrefetcher(const BaseCacheParams *p)
44 : size(p->prefetcher_size), pageStop(!p->prefetch_past_page),
45 serialSquash(p->prefetch_serial_squash),
46 cacheCheckPush(p->prefetch_cache_check_push),
46 only_data(p->prefetch_data_accesses_only)
47 onlyData(p->prefetch_data_accesses_only)
47{
48}
49
50void
51BasePrefetcher::setCache(BaseCache *_cache)
52{
53 cache = _cache;
54 blkSize = cache->getBlockSize();
48{
49}
50
51void
52BasePrefetcher::setCache(BaseCache *_cache)
53{
54 cache = _cache;
55 blkSize = cache->getBlockSize();
56 _name = cache->name() + "-pf";
55}
56
57void
58BasePrefetcher::regStats(const std::string &name)
59{
60 pfIdentified
61 .name(name + ".prefetcher.num_hwpf_identified")
62 .desc("number of hwpf identified")

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94
95 pfSpanPage
96 .name(name + ".prefetcher.num_hwpf_span_page")
97 .desc("number of hwpf spanning a virtual page")
98 ;
99
100 pfSquashed
101 .name(name + ".prefetcher.num_hwpf_squashed_from_miss")
57}
58
59void
60BasePrefetcher::regStats(const std::string &name)
61{
62 pfIdentified
63 .name(name + ".prefetcher.num_hwpf_identified")
64 .desc("number of hwpf identified")

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96
97 pfSpanPage
98 .name(name + ".prefetcher.num_hwpf_span_page")
99 .desc("number of hwpf spanning a virtual page")
100 ;
101
102 pfSquashed
103 .name(name + ".prefetcher.num_hwpf_squashed_from_miss")
102 .desc("number of hwpf that got squashed due to a miss aborting calculation time")
104 .desc("number of hwpf that got squashed due to a miss "
105 "aborting calculation time")
103 ;
104}
105
106inline bool
107BasePrefetcher::inCache(Addr addr)
108{
109 if (cache->inCache(addr)) {
110 pfCacheHit++;

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121 return true;
122 }
123 return false;
124}
125
126PacketPtr
127BasePrefetcher::getPacket()
128{
106 ;
107}
108
109inline bool
110BasePrefetcher::inCache(Addr addr)
111{
112 if (cache->inCache(addr)) {
113 pfCacheHit++;

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124 return true;
125 }
126 return false;
127}
128
129PacketPtr
130BasePrefetcher::getPacket()
131{
129 DPRINTF(HWPrefetch, "%s:Requesting a hw_pf to issue\n", cache->name());
132 DPRINTF(HWPrefetch, "Requesting a hw_pf to issue\n");
130
131 if (pf.empty()) {
133
134 if (pf.empty()) {
132 DPRINTF(HWPrefetch, "%s:No HW_PF found\n", cache->name());
135 DPRINTF(HWPrefetch, "No HW_PF found\n");
133 return NULL;
134 }
135
136 PacketPtr pkt;
136 return NULL;
137 }
138
139 PacketPtr pkt;
137 bool keepTrying = false;
140 bool keep_trying = false;
138 do {
139 pkt = *pf.begin();
140 pf.pop_front();
141 if (!cacheCheckPush) {
141 do {
142 pkt = *pf.begin();
143 pf.pop_front();
144 if (!cacheCheckPush) {
142 keepTrying = cache->inCache(pkt->getAddr());
145 keep_trying = cache->inCache(pkt->getAddr());
143 }
146 }
147
148 if (keep_trying) {
149 DPRINTF(HWPrefetch, "addr 0x%x in cache, skipping\n",
150 pkt->getAddr());
151 delete pkt->req;
152 delete pkt;
153 }
154
144 if (pf.empty()) {
145 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
155 if (pf.empty()) {
156 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
146 if (keepTrying) return NULL; //None left, all were in cache
157 if (keep_trying) {
158 return NULL; // None left, all were in cache
159 }
147 }
160 }
148 } while (keepTrying);
161 } while (keep_trying);
149
150 pfIssued++;
162
163 pfIssued++;
164 assert(pkt != NULL);
165 DPRINTF(HWPrefetch, "returning 0x%x\n", pkt->getAddr());
151 return pkt;
152}
153
166 return pkt;
167}
168
154void
155BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time)
169
170Tick
171BasePrefetcher::notify(PacketPtr &pkt, Tick time)
156{
172{
157 if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && only_data))
158 {
159 //Calculate the blk address
160 Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);
173 if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && onlyData)) {
174 // Calculate the blk address
175 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
161
176
162 //Check if miss is in pfq, if so remove it
163 std::list<PacketPtr>::iterator iter = inPrefetch(blkAddr);
177 // Check if miss is in pfq, if so remove it
178 std::list<PacketPtr>::iterator iter = inPrefetch(blk_addr);
164 if (iter != pf.end()) {
179 if (iter != pf.end()) {
165 DPRINTF(HWPrefetch, "%s:Saw a miss to a queued prefetch, removing it\n", cache->name());
180 DPRINTF(HWPrefetch, "Saw a miss to a queued prefetch addr: "
181 "0x%x, removing it\n", blk_addr);
166 pfRemovedMSHR++;
182 pfRemovedMSHR++;
183 delete (*iter)->req;
184 delete (*iter);
167 pf.erase(iter);
168 if (pf.empty())
169 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
170 }
171
185 pf.erase(iter);
186 if (pf.empty())
187 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
188 }
189
172 //Remove anything in queue with delay older than time
173 //since everything is inserted in time order, start from end
174 //and work until pf.empty() or time is earlier
175 //This is done to emulate Aborting the previous work on a new miss
176 //Needed for serial calculators like GHB
190 // Remove anything in queue with delay older than time
191 // since everything is inserted in time order, start from end
192 // and work until pf.empty() or time is earlier
193 // This is done to emulate Aborting the previous work on a new miss
194 // Needed for serial calculators like GHB
177 if (serialSquash) {
178 iter = pf.end();
179 iter--;
180 while (!pf.empty() && ((*iter)->time >= time)) {
181 pfSquashed++;
195 if (serialSquash) {
196 iter = pf.end();
197 iter--;
198 while (!pf.empty() && ((*iter)->time >= time)) {
199 pfSquashed++;
182 pf.pop_back();
200 DPRINTF(HWPrefetch, "Squashing old prefetch addr: 0x%x\n",
201 (*iter)->getAddr());
202 delete (*iter)->req;
203 delete (*iter);
204 pf.erase(iter);
183 iter--;
184 }
185 if (pf.empty())
186 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
187 }
188
189
190 std::list<Addr> addresses;
191 std::list<Tick> delays;
192 calculatePrefetch(pkt, addresses, delays);
193
205 iter--;
206 }
207 if (pf.empty())
208 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
209 }
210
211
212 std::list<Addr> addresses;
213 std::list<Tick> delays;
214 calculatePrefetch(pkt, addresses, delays);
215
194 std::list::iterator addr = addresses.begin();
195 std::list::iterator delay = delays.begin();
196 while (addr != addresses.end())
197 {
198 DPRINTF(HWPrefetch, "%s:Found a pf canidate, inserting into prefetch queue\n", cache->name());
199 //temp calc this here...
216 std::list<Addr>::iterator addrIter = addresses.begin();
217 std::list<Tick>::iterator delayIter = delays.begin();
218 for (; addrIter != addresses.end(); ++addrIter, ++delayIter) {
219 Addr addr = *addrIter;
220
200 pfIdentified++;
221 pfIdentified++;
201 //create a prefetch memreq
202 Request * prefetchReq = new Request(*addr, blkSize, 0);
203 PacketPtr prefetch;
204 prefetch = new Packet(prefetchReq, MemCmd::HardPFReq, -1);
205 prefetch->allocate();
206 prefetch->req->setThreadContext(pkt->req->contextId(),
207 pkt->req->threadId());
208
222
209 prefetch->time = time + (*delay); //@todo ADD LATENCY HERE
210 //... initialize
223 DPRINTF(HWPrefetch, "Found a pf candidate addr: 0x%x, "
224 "inserting into prefetch queue with delay %d time %d\n",
225 addr, *delayIter, time);
211
226
212 //Check if it is already in the cache
213 if (cacheCheckPush) {
214 if (cache->inCache(prefetch->getAddr())) {
215 addr++;
216 delay++;
217 continue;
218 }
227 // Check if it is already in the cache
228 if (cacheCheckPush && cache->inCache(addr)) {
229 DPRINTF(HWPrefetch, "Prefetch addr already in cache\n");
230 continue;
219 }
220
231 }
232
221 //Check if it is already in the miss_queue
222 if (cache->inMissQueue(prefetch->getAddr())) {
223 addr++;
224 delay++;
233 // Check if it is already in the miss_queue
234 if (cache->inMissQueue(addr)) {
235 DPRINTF(HWPrefetch, "Prefetch addr already in miss queue\n");
225 continue;
226 }
227
236 continue;
237 }
238
228 //Check if it is already in the pf buffer
229 if (inPrefetch(prefetch->getAddr()) != pf.end()) {
239 // Check if it is already in the pf buffer
240 if (inPrefetch(addr) != pf.end()) {
230 pfBufferHit++;
241 pfBufferHit++;
231 addr++;
232 delay++;
242 DPRINTF(HWPrefetch, "Prefetch addr already in pf buffer\n");
233 continue;
234 }
235
243 continue;
244 }
245
236 //We just remove the head if we are full
237 if (pf.size() == size)
238 {
239 DPRINTF(HWPrefetch, "%s:Inserting into prefetch queue, it was full removing oldest\n", cache->name());
246 // create a prefetch memreq
247 Request *prefetchReq = new Request(*addrIter, blkSize, 0);
248 PacketPtr prefetch =
249 new Packet(prefetchReq, MemCmd::HardPFReq, Packet::Broadcast);
250 prefetch->allocate();
251 prefetch->req->setThreadContext(pkt->req->contextId(),
252 pkt->req->threadId());
253
254 prefetch->time = time + (*delayIter); // @todo ADD LATENCY HERE
255
256 // We just remove the head if we are full
257 if (pf.size() == size) {
240 pfRemovedFull++;
258 pfRemovedFull++;
259 PacketPtr old_pkt = *pf.begin();
260 DPRINTF(HWPrefetch, "Prefetch queue full, "
261 "removing oldest 0x%x\n", old_pkt->getAddr());
262 delete old_pkt->req;
263 delete old_pkt;
241 pf.pop_front();
242 }
243
244 pf.push_back(prefetch);
264 pf.pop_front();
265 }
266
267 pf.push_back(prefetch);
245
246 //Make sure to request the bus, with proper delay
247 cache->requestMemSideBus(BaseCache::Request_PF, prefetch->time);
248
249 //Increment through the list
250 addr++;
251 delay++;
252 }
253 }
268 }
269 }
270
271 return pf.empty() ? 0 : pf.front()->time;
254}
255
256std::list<PacketPtr>::iterator
257BasePrefetcher::inPrefetch(Addr address)
258{
272}
273
274std::list<PacketPtr>::iterator
275BasePrefetcher::inPrefetch(Addr address)
276{
259 //Guaranteed to only be one match, we always check before inserting
277 // Guaranteed to only be one match, we always check before inserting
260 std::list<PacketPtr>::iterator iter;
278 std::list<PacketPtr>::iterator iter;
261 for (iter=pf.begin(); iter != pf.end(); iter++) {
279 for (iter = pf.begin(); iter != pf.end(); iter++) {
262 if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) {
263 return iter;
264 }
265 }
266 return pf.end();
267}
268
280 if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) {
281 return iter;
282 }
283 }
284 return pf.end();
285}
286
269
287bool
288BasePrefetcher::samePage(Addr a, Addr b)
289{
290 return roundDown(a, TheISA::VMPageSize) == roundDown(b, TheISA::VMPageSize);
291}