base.cc (13624:3d8220c2d41d) base.cc (13717:11e81e2a98bd)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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67 : address(addr), pc(pfi.pc), masterId(pfi.masterId), validPC(pfi.validPC),
68 secure(pfi.secure)
69{
70}
71
72void
73BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
74{
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 58 unchanged lines hidden (view full) ---

67 : address(addr), pc(pfi.pc), masterId(pfi.masterId), validPC(pfi.validPC),
68 secure(pfi.secure)
69{
70}
71
72void
73BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
74{
75 parent.probeNotify(pkt);
75 if (isFill) {
76 parent.notifyFill(pkt);
77 } else {
78 parent.probeNotify(pkt);
79 }
76}
77
78BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
79 : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
80 lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
81 onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
82 masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
83 prefetchOnAccess(p->prefetch_on_access),

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219 /**
220 * If no probes were added by the configuration scripts, connect to the
221 * parent cache using the probe "Miss". Also connect to "Hit", if the
222 * cache is configured to prefetch on accesses.
223 */
224 if (listeners.empty() && cache != nullptr) {
225 ProbeManager *pm(cache->getProbeManager());
226 listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
80}
81
82BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
83 : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
84 lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
85 onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
86 masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
87 prefetchOnAccess(p->prefetch_on_access),

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223 /**
224 * If no probes were added by the configuration scripts, connect to the
225 * parent cache using the probe "Miss". Also connect to "Hit", if the
226 * cache is configured to prefetch on accesses.
227 */
228 if (listeners.empty() && cache != nullptr) {
229 ProbeManager *pm(cache->getProbeManager());
230 listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
231 listeners.push_back(new PrefetchListener(*this, pm, "Fill", true));
227 if (prefetchOnAccess) {
228 listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
229 }
230 }
231}
232
233void
234BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
235{
236 ProbeManager *pm(obj->getProbeManager());
237 listeners.push_back(new PrefetchListener(*this, pm, name));
238}
232 if (prefetchOnAccess) {
233 listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
234 }
235 }
236}
237
238void
239BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
240{
241 ProbeManager *pm(obj->getProbeManager());
242 listeners.push_back(new PrefetchListener(*this, pm, name));
243}