base.cc (12727:56c23b54bcb1) base.cc (13416:d90887d0c889)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46 * Hardware Prefetcher Definition.
47 */
48
49#include "mem/cache/prefetch/base.hh"
50
51#include <cassert>
52
53#include "base/intmath.hh"
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46 * Hardware Prefetcher Definition.
47 */
48
49#include "mem/cache/prefetch/base.hh"
50
51#include <cassert>
52
53#include "base/intmath.hh"
54#include "cpu/base.hh"
54#include "mem/cache/base.hh"
55#include "params/BasePrefetcher.hh"
56#include "sim/system.hh"
57
55#include "mem/cache/base.hh"
56#include "params/BasePrefetcher.hh"
57#include "sim/system.hh"
58
59void
60BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
61{
62 parent.probeNotify(pkt);
63}
64
58BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
65BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
59 : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
66 : ClockedObject(p), listeners(), cache(nullptr), blkSize(0), lBlkSize(0),
60 system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
61 onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
62 masterId(system->getMasterId(this)),
67 system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
68 onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
69 masterId(system->getMasterId(this)),
63 pageBytes(system->getPageBytes())
70 pageBytes(system->getPageBytes()),
71 prefetchOnAccess(p->prefetch_on_access)
64{
65}
66
67void
68BasePrefetcher::setCache(BaseCache *_cache)
69{
70 assert(!cache);
71 cache = _cache;

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158 return a & (pageBytes - 1);
159}
160
161Addr
162BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
163{
164 return page + (blockIndex << lBlkSize);
165}
72{
73}
74
75void
76BasePrefetcher::setCache(BaseCache *_cache)
77{
78 assert(!cache);
79 cache = _cache;

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166 return a & (pageBytes - 1);
167}
168
169Addr
170BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
171{
172 return page + (blockIndex << lBlkSize);
173}
174
175void
176BasePrefetcher::probeNotify(const PacketPtr &pkt)
177{
178 // Don't notify prefetcher on SWPrefetch, cache maintenance
179 // operations or for writes that we are coaslescing.
180 if (pkt->cmd.isSWPrefetch()) return;
181 if (pkt->req->isCacheMaintenance()) return;
182 if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
183 notify(pkt);
184}
185
186void
187BasePrefetcher::regProbeListeners()
188{
189 /**
190 * If no probes were added by the configuration scripts, connect to the
191 * parent cache using the probe "Miss". Also connect to "Hit", if the
192 * cache is configured to prefetch on accesses.
193 */
194 if (listeners.empty() && cache != nullptr) {
195 ProbeManager *pm(cache->getProbeManager());
196 listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
197 if (prefetchOnAccess) {
198 listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
199 }
200 }
201}
202
203void
204BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
205{
206 ProbeManager *pm(obj->getProbeManager());
207 listeners.push_back(new PrefetchListener(*this, pm, name));
208}